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order this document by MC68CK338TS/d m this document contains information on a new product. specifications and information herein are subject to change without notice. ?motorola inc., 1996 motorola semiconductor technical data mc68ck338 technical summary 32-bit modular microcontroller 1 introduction the mc68ck338, a highly-integrated 32-bit microcontroller, combines high-performance data manipu- lation capabilities with powerful peripheral subsystems. the mcu is built up from standard modules that interface through a common intermodule bus (imb). standardization facilitates rapid development of devices tailored for specific applications. the mcu incorporates a low-power 32-bit cpu (cpu32l), a low-power system integration module (siml), a queued serial module (qsm), and a configurable timer module 6 (ctm6). the mcu clock can either be synthesized from an external reference or input directly. operation with a 32.768 khz reference frequency is standard. the maximum system clock speed is 14.4 mhz. system hardware and software allow changes in clock rate during operation. because mcu operation is fully static, register and memory contents are not affected by clock rate changes. high-density complementary metal-oxide semiconductor (hcmos) architecture and 3v nominal oper- ation make the basic power consumption of the mcu low. power consumption can be minimized by either stopping the system clock, or alternatively, stopping the system clock only at the cpu32l, and allowing the other modules to continue operation. the cpu32 instruction set includes a low-power stop (lpstop) command that allows either of these power saving modes. the ctm6 includes new features such as a port i/o submodule, a 64-byte ram submodule and a real time clock submodule. refer to the motorola microcontroller technologies group web page at http://www.mcu.sps.mot.com for the most current listing of device errata and customer information. table 1 ordering information package type frequency (mhz) voltage temperature package order quantity order number 144?in tqfp 14.4 mhz 2.7v to 3.6v ?40 to + 85 c 2 pc tray 60 pc tray 300 pc tray spmc68ck338cpv14 mc68ck338cpv14 mc68ck338cpv14b1
section page motorola mc68ck338 2 MC68CK338TS/d 1 introduction 1 1.1 features ...................................................................................................................................... 3 1.2 block diagram ............................................................................................................................. 4 1.3 pin assignments .......................................................................................................................... 5 1.4 address map ............................................................................................................................... 6 1.5 intermodule bus .......................................................................................................................... 6 2 signal descriptions 7 2.1 pin characteristics ...................................................................................................................... 7 2.2 mcu power connections ............................................................................................................ 8 2.3 mcu driver types ....................................................................................................................... 8 2.4 signal characteristics .................................................................................................................. 9 2.5 signal function .......................................................................................................................... 10 3 low-power system integration module 12 3.1 overview ................................................................................................................................... 12 3.2 system configuration block ...................................................................................................... 14 3.3 system clock ............................................................................................................................ 16 3.4 system protection block ........................................................................................................... 22 3.5 external bus interface ............................................................................................................... 26 3.6 chip-selects .............................................................................................................................. 30 3.7 general-purpose input/output .................................................................................................. 38 3.8 resets ....................................................................................................................................... 41 3.9 interrupts ................................................................................................................................... 44 3.10 factory test block ..................................................................................................................... 47 4 low-power central processor unit 48 4.1 overview ................................................................................................................................... 48 4.2 programming model .................................................................................................................. 48 4.3 status register .......................................................................................................................... 50 4.4 data types ................................................................................................................................ 51 4.5 addressing modes ..................................................................................................................... 51 4.6 instruction set summary ........................................................................................................... 51 4.7 background debugging mode ................................................................................................... 56 5 queued serial module 57 5.1 overview ................................................................................................................................... 57 5.2 address map ............................................................................................................................. 58 5.3 pin function .............................................................................................................................. 59 5.4 qsm registers .......................................................................................................................... 59 5.5 qspi submodule ....................................................................................................................... 64 5.6 sci submodule ......................................................................................................................... 72 6 configurable timer module 6 78 6.1 overview ................................................................................................................................... 78 6.2 address map ............................................................................................................................. 80 6.3 time base bus system ............................................................................................................. 82 6.4 bus interface unit submodule (biusm) .................................................................................... 84 6.5 counter prescaler submodule (cpsm) .................................................................................... 85 6.6 clock sources for counter submodules ................................................................................... 87 6.7 free-running counter submodule (fcsm) .............................................................................. 87 6.8 modulus counter submodule (mcsm) ..................................................................................... 90 6.9 single action submodule (sasm) ............................................................................................. 93 6.10 double-action submodule (dasm) ........................................................................................... 97 6.11 real-time clock submodule (rtcsm) with low-power oscillator ........................................ 104 6.12 parallel port i/o submodule (piosm) ..................................................................................... 107 6.13 static ram submodule (ramsm) .......................................................................................... 108 6.14 rtcsm and ramsm standby operation ............................................................................... 108 6.15 ctm6 interrupts ...................................................................................................................... 109 7 electrical characteristics 111 table of contents
mc68ck338 motorola MC68CK338TS/d 3 1.1 features ?modular architecture ?low-power central processing unit (cpu32l) ?virtual memory implementation ?loop mode of instruction execution ?improved exception handling for controller applications ?table lookup and interpolate instruction ?cpu-only lpstop operation/normal mcu lpstop operation ?low-power system integration module (siml) ?external bus support ?twelve programmable chip-select outputs ?system protection logic ?on-chip pll for system clock ?watchdog timer, clock monitor, and bus monitor ?expanded lpstop operation ?queued serial module (qsm) ?enhanced serial communication interface (sci) ?queued serial peripheral interface (qspi) ?dual function i/o ports ?configurable timer module 6 (ctm6) ?one bus interface unit submodule (biusm) ?one counter prescaler submodule (cpsm) ?three modulus counter submodules (mcsm) ?one free-running counter submodule (fcsm) ?eleven double action submodules (dasm) ?four (eight channels) single action submodules (sasm) ?one real time clock submodule (rtcsm) ?one port i/o submodule (piosm) ?two 32-byte ram submodules (ramsm)
motorola mc68ck338 4 MC68CK338TS/d 1.2 block diagram figure 1 mc68ck338 block diagram 1 fcsm 3 mcsm 11 dasm 4 sasm 338 block pqs5/pcs2 pqs7/txd pqs4/pcs1 pqs6/pcs3 cpu32l qsm imb ctm6 pqs0/miso pqs1/mosi pqs2/sck portqs txd pcs2 sck miso mosi control pcs1 pqs3/pcs0/ss pcs0 rxd pcs3 control bkpt /dsclk ifetch /dsi ipipe /dso freeze dsi dso dsclk ipipe ifetch bkpt irq[7:1] addr[23:0] control port f control fc2 fc1 fc0 bg br bgack modclk addr[23:19] clock ebi cs[10:0] br /cs0 bg /cs1 bgack /cs2 r/w reset halt berr clkout xtal extal chip selects csboot addr[18:0] data[15:0] data[15:0] quot test freeze/quot tsc control tsc pc0/fc0/cs3 pc1/fc1/cs4 pc2/fc2/cs5 pc3/addr19/cs6 pc4/addr20/cs7 pc5/addr21/cs8 pc6/addr22/cs9 addr23/cs10 pf7/irq7 pf6/irq6 pf5/irq5 pf4/irq4 pf3/irq3 pf2/irq2 pf1/irq1 pf0/modclk control port e siz1 pe7/siz1 siz0 pe6/siz0 dsack0 pe0/dsack0 dsack1 pe1/dsack1 avec pe2/avec rmc pe3/rmc as pe5/as ds pe4/ds ctd[10:4] ctm31l cts18b ctd[29:26] xrtc ctio[5:0] ctm31l ctd[10:4] ctio[5:0] xrtc cts18b cts18a cts18a ctd[29:26] port c xfc vddsyn ss exrtc exrtc vrtc vrtc 1 piosm 64 bytes 1 rtcsm 2 ramsm cts24b cts24b cts24a cts24a cts14b cts14b cts14a cts14a port ct vssrtcosc vssrtcosc vssrtcosc vssrtcosc
mc68ck338 motorola MC68CK338TS/d 5 1.3 pin assignments figure 2 mc68ck338 pin assignments mc68ck338 nc vsse ctd5 ctd4 vssrtcosc xrtc exrtc vssrtcosc ctio2 ctio3 cts14b cts14a ctio4 ctio5 cts18b cts18a cts24b cts24a vssi vddi ctd29 ctd28 ctd27 ctd26 ctm31l addr23/cs10 addr22/cs9 addr21/cs8 addr20/cs7 addr19/cs6 fc2/cs5 fc1/cs4 vsse nc nc nc nc nc nc vsse addr17 addr18 ipipe /dso ifetch /dsi bkpt /dsclk tsc freeze/quot vssi xtal vddsyn extal vddi xfc vdde clkout vsse reset halt berr irq7 irq6 irq5 irq4 irq3 irq2 irq1 modclk r/w vsse nc nc nc vdde nc nc nc fc0/cs3 bgack /cs2 bg /cs1 br /cs0 csboot data0 data1 data2 data3 data4 data5 data6 data7 vssi data8 data9 data10 data11 data12 data13 data14 data15 addr0 dsack0 dsack1 avec rmc ds as siz0 siz1 vdde vdde ctd6 ctd7 ctd8 ctd9 ctd10 ctio1 ctio0 vrtc miso mosi sck pcs0/ss pcs1 pcs2 pcs3 txd vssi rxd addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 addr16 vdde 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 104 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 338 144-pin qfp
motorola mc68ck338 6 MC68CK338TS/d 1.4 address map figure 3 shows a map of the mcu internal addresses. unimplemented blocks are mapped externally. figure 3 mc68ck338 address map 1.5 intermodule bus the imb is a standardized bus developed to facilitate design and operation of modular microcontrollers. it contains circuitry that supports exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. the standardized modules in the mcu communicate with one another and with external components via the imb. the imb uses 24 address lines and 16 data lines. 338 address map $yffdff $yffc00 $yffa7f $yffa00 $yff5ff $yff400 siml qsm ctm6 y = m111, where m is the state of the module mapping (mm) bit in the siml configuration register. 512 bytes 128 bytes 512 bytes
mc68ck338 motorola MC68CK338TS/d 7 2 signal descriptions 2.1 pin characteristics table 2 shows mcu pins and their characteristics. all inputs detect cmos logic levels. all inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. re- fer to table 4 for a description of output drivers. an entry in the discrete i/o column of table 2 indicates that a pin has an alternate i/o function. the port designation is given when it applies. refer to figure 1 for information about port organization. table 2 mcu pin characteristics pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation addr23/cs10 a yes no addr[22:19]/cs[9:6] a yes no o pc[6:3] addr[18:0] a yes no as b yes no i/o pe5 a vec b yes no i/o pe2 berr b yes 1 no bg /cs1 b bga ck /cs2 b yes no bkpt /dsclk yes yes br /cs0 b yes no clkout a csboo t b ctd[29:26] ao yes yes i/o ctd[10:4] ao yes yes i/o ctio[5:0] a yes yes i/o ctm31l a yes yes i cts24[b:a] a yes yes i/o cts18[b:a] a yes yes i/o cts14[b:a] a yes yes i/o data[15:0] aw yes 2 no ds b yes no i/o pe4 dsa ck[1:0] b yes no i/o pe[1:0] dsi/ifetch a yes yes dso/ipipe a exrtc yes extal yes fc[2:0]/cs[5:3] a yes no o pc[2:0] freeze/quot a hal t bo yes 1 no irq[7:1] b yes yes i/o pf[7:1] miso bo yes 2 yes i/o pqs0 modclk b yes 2 no i/o pf0 mosi bo yes 2 yes i/o pqs1
motorola mc68ck338 8 MC68CK338TS/d 2.2 mcu power connections 2.3 mcu driver types notes: 1. hal t and berr synchronized only if late hal t or berr . 2. data[15:0] synchronized during reset only. modclk and qsm pins synchronized only if used as port i/o pins. pcs0/ss bo yes 2 yes i/o pqs3 pcs[3:1] bo yes 2 yes i/o pqs[6:4] reset bo yes yes rmc a yes yes i/o pe3 r/w a yes no rxd no yes sck bo yes 2 yes i/o pqs2 siz[1:0] b yes no i/o pe[7:6] tsc yes yes txd bo yes 2 yes i/o pqs7 xfc xrtc xtal table 3 mcu power connections v ddsyn clock synthesizer v dde , v sse external periphery power (source and drain) v ddi , v ssi internal module power (source and drain) v rtc rtcsm/ramsm standby power v ssrtcosc ground connection for real-time clock oscillator table 4 mcu output driver types type description a output-only signals that are always driven; no external pull-up required ao type a output that can be operated in an open drain mode aw type a output with weak p-channel pull-up during reset b three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time. an external holding resistor is required to maintain logic level while the pin is in the high-impedance state. bw type b output with weak p-channel pull-up during reset bo type b output that can be operated in an open-drain mode table 2 mcu pin characteristics (continued) pin mnemonic output driver input synchronized input hysteresis discrete i/o port designation
mc68ck338 motorola MC68CK338TS/d 9 2.4 signal characteristics table 5 mcu signal characteristics signal name mcu module signal type active state addr[23:0] siml bus as siml output 0 a vec siml input 0 berr siml input 0 bg siml output 0 bga ck siml input 0 bkpt cpu32l input 0 br siml input 0 clkout siml output cs[10:0] siml output 0 csboo t siml output 0 ctd[29:26] ctm6 input/output ctd[10:4] ctm6 input/output ctio[5:0] ctm6 input/output ctm31l ctm6 input cts24[b:a] ctm6 input/output cts18[b:a] ctm6 input/output cts14[b:a] ctm6 input/output data[15:0] siml bus ds siml output 0 dsa ck[1:0] siml input 0 dsclk cpu32l input serial clock dsi cpu32l input dso cpu32l output exrtc ctm6 input extal siml input fc[2:0] siml output freeze siml output 1 hal t siml input/output 0 ifetch cpu32l output ipipe cpu32l output irq[7:1] siml input 0 miso qsm input/output modclk siml input mosi qsm input/output pc[6:0] siml output pcs[3:0] qsm input/output pe[7:0] siml input/output pf[7:0] siml input/output pqs[7:0] qsm input/output quot siml output
motorola mc68ck338 10 MC68CK338TS/d 2.5 signal function reset siml input/output 0 rmc siml output 0 r/w siml output 0 rxd qsm input sck qsm input/output siz[1:0] siml output ss qsm input 0 tsc siml input txd qsm output xfc siml input xrtc ctm6 output xtal siml output table 6 mcu signal function signal name mnemonic function address bus addr[23:0] 24-bit address bus address strobe as indicates that a valid address is on the address bus autovector a vec requests an automatic vector during interrupt acknowledge bus error berr signals a bus error to the cpu bus grant bg indicates that the mcu has relinquished the bus bus grant acknowledge bga ck indicates that an external device has assumed bus mastership breakpoint bkpt signals a hardware breakpoint to the cpu bus request br indicates that an external device requires bus mastership system clockout clkout system clock output chip selects cs[10:0] select external devices at programmed addresses boot chip select csboo t chip select for external boot startup rom configurable timer double-action ctd[29:26], ctd[10:4] double-action submodule (dasm) signals. can also be used as general purpose i/o pins configurable timer modulus counter load ctm31l external load for modulus counter. can also be used as general purpose input rtc configurable timer oscillator exrtc, xrtc ctm real time clock oscillator input/output configurable timer port input/output ctio[5:0] general-purpose i/o pins configurable timer single-action cts24[b:a] cts18[b:a] cts14[b:a] single-action submodule (sasm) signals. can also be used as general purpose i/o pins crystal oscillator extal, xtal connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used data bus data[15:0] 16-bit data bus table 5 mcu signal characteristics (continued) signal name mcu module signal type active state
mc68ck338 motorola MC68CK338TS/d 11 data strobe ds indicates that an external device should place valid data on the data bus during a read cycle and that valid data has been placed on the bus by the cpu during a write cycle data and size acknowledge dsa ck[1:0] acknowledges to the siml that data has been received for a write cycle, or that data is valid on the data bus for a read cycle development serial in, out, clock dsi, dso, dsclk serial i/o and clock for background debugging mode function codes fc[2:0] identify processor state and current address space freeze freeze indicates that the cpu has entered background mode halt hal t suspend external bus activity instruction pipeline ifetch , ipipe indicate instruction pipeline activity interrupt request level irq[7:1] request interrupt service from the cpu master in slave out miso serial input to qspi in master mode; serial output from qspi in slave mode clock mode select modclk selects system clock source master out slave in mosi serial output from qspi in master mode; serial input to qspi in slave mode port c pc[6:0] siml digital output signals peripheral chip select pcs[3:0] qspi peripheral chip selects port e pe[7:0] siml digital input or output port signals port f pf[7:0] siml digital input or output port signals port qs pqs[7:0] qsm digital i/o port signals quotient out quot provides the quotient bit of the polynomial divider reset reset system reset read-modify-write cycle rmc indicates an indivisible read-modify-write instruction read/write r/w indicates the direction of data transfer on the bus sci receive data rxd serial input to the sci qspi serial clock sck clock output from qspi in master mode; clock input to qspi in slave mode size siz[1:0] indicates the number of bytes to be transferred during a bus cycle slave select ss causes serial transmission when qspi is in slave mode. causes mode fault in master mode three-state control tsc places all output drivers in a high-impedance state sci transmit data txd serial output from the sci external filter capacitor xfc connection for external phase-locked loop filter capacitor table 6 mcu signal function (continued) signal name mnemonic function
motorola mc68ck338 12 MC68CK338TS/d 3 low-power system integration module the low-power system integration module (siml) consists of five functional blocks that control system startup, initialization, configuration, and the external bus. figure 4 shows the siml block diagram. figure 4 siml block diagram 3.1 overview the system configuration block controls mcu configuration and operating mode. the clock synthesizer generates clock signals used by the siml, other imb modules, and external de- vices. in addition, a periodic interrupt generator supports execution of time-critical control routines. the system protection block provides bus and software watchdog monitors. the chip-select block provides eleven general-purpose chip-select signals and a boot rom chip-select signal. both general-purpose and boot rom chip-select signals have associated base address regis- ters and option registers. the external bus interface handles the transfer of information between imb modules and external ad- dress space. the system test block incorporates hardware necessary for testing the mcu. it is used to perform fac- tory tests, and its use in normal applications is not supported. table 7 shows the siml address map, which occupies 128 bytes. unused registers within the 128-byte address space return zeros when read. the ?ccess?column indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the supv bit in the simlcr. 338 s(c)im block system configuration clock synthesizer chip-selects external bus interface factory test clkout extal modclk chip-selects external bus reset tsc freeze/quot xtal system protection
mc68ck338 motorola MC68CK338TS/d 13 table 7 siml address map access address 1 15 8 7 0 s $yffa00 siml module configuration register (simlcr) s $yffa02 siml test register (simltr) s $yffa04 clock synthesizer control register (syncr) s $yffa06 not used reset status register (rsr) s $yffa08 siml test register e (simltre) $yffa0a not used $yffa0c not used $yffa0e not used s/u $yffa10 not used port e data (porte0) s/u $yffa12 not used port e data (porte1) s/u $yffa14 not used port e data direction (ddre) s $yffa16 not used port e pin assignment (pepar) s/u $yffa18 not used port f data (portf0) s/u $yffa1a not used port f data (portf1) s/u $yffa1c not used port f data direction (ddrf) s $yffa1e not used port f pin assignment (pfpar) s $yffa20 not used system protection control (sypcr) s $yffa22 periodic interrupt control register (picr) s $yffa24 periodic interrupt timer register (pitr) s $yffa26 not used software service (swsr) s $yffa28 not used s $yffa2a not used s $yffa2c not used s $yffa2e not used s $yffa30 test module master shift a (tstmsra) s $yffa32 test module master shift b (tstmsrb) s $yffa34 test module shift count (tstsc) s $yffa36 test module repetition counter (tstrc) s $yffa38 test module control (creg) s/u $yffa3a test module distributed register (dreg) $yffa3c not used $yffa3e not used s/u $yffa40 not used port c data (portc) $yffa42 not used s $yffa44 chip-select pin assignment (cspar0) s $yffa46 chip-select pin assignment (cspar1) s $yffa48 chip-select base boot (csbarbt) s $yffa4a chip-select option boot (csorbt) s $yffa4c chip-select base 0 (csbar0) s $yffa4e chip-select option 0 (csor0) s $yffa50 chip-select base 1 (csbar1)
motorola mc68ck338 14 MC68CK338TS/d 3.2 system configuration block this functional block provides configuration control for the entire mcu. it also performs interrupt arbi- tration, bus monitoring, and system test functions. 3.2.1 mcu configuration the siml controls mcu configuration during normal operation and during internal testing. the siml configuration register controls system configuration. it can be read or written at any time, ex- cept for the module mapping (mm) bit, which can be written only once. notes: 1. y = m111, where m is the logic state of the module mapping (mm) bit in the simlcr. s $yffa52 chip-select option 1 (csor1) s $yffa54 chip-select base 2 (csbar2) s $yffa56 chip-select option 2 (csor2) s $yffa58 chip-select base 3 (csbar3) s $yffa5a chip-select option 3 (csor3) s $yffa5c chip-select base 4 (csbar4) s $yffa5e chip-select option 4 (csor4) s $yffa60 chip-select base 5 (csbar5) s $yffa62 chip-select option 5 (csor5) s $yffa64 chip-select base 6 (csbar6) s $yffa66 chip-select option 6 (csor6) s $yffa68 chip-select base 7 (csbar7) s $yffa6a chip-select option 7 (csor7) s $yffa6c chip-select base 8 (csbar8) s $yffa6e chip-select option 8 (csor8) s $yffa70 chip-select base 9 (csbar9) s $yffa72 chip-select option 9 (csor9) s $yffa74 chip-select base 10 (csbar10) s $yffa76 chip-select option 10 (csor10) $yffa78 not used $yffa7a not used $yffa7c not used $yffa7e not used simlcr siml configuration register $yffa00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 exoff frzsw frzbm 0 slven 0 shen supv mm 0 0 iarb[3:0] reset: 0 0 0 0 data11 0 0 0 1 1 0 0 1 1 1 1 table 7 siml address map (continued) access address 1 15 8 7 0
mc68ck338 motorola MC68CK338TS/d 15 exoff ?external clock off 0 = the clkout pin is driven by the mcu system clock. 1 = the clkout pin is placed in a high-impedance state. frzsw ?freeze software enable 0 = when freeze is asserted, the software watchdog and periodic interrupt timer counters con- tinue to run. 1 = when freeze is asserted, the software watchdog and periodic interrupt timer counters are dis- abled, preventing interrupts while the mcu is in background debug mode. frzbm ?freeze bus monitor enable 0 = when freeze is asserted, the bus monitor continues to operate. 1 = when freeze is asserted, the bus monitor is disabled. slven ?factory test mode enabled this bit is a read-only status bit that reflects the state of data11 during reset. 0 = imb is not available to an external master. 1 = an external bus master has direct access to the imb. shen[1:0] ?show cycle enable this field determines what the ebi does with the external bus during internal transfer operations. a show cycle allows internal transfers to be externally monitored. table 8 shows whether show cycle data is driven externally, and whether external bus arbitration can occur. to prevent bus conflict, external peripherals must not be enabled during show cycles. supv ?supervisor/unrestricted data space the supv bit places the siml global registers in either supervisor or user data space. 0 = registers with access controlled by the supv bit are accessible in either supervisor or user data space. 1 = registers with access controlled by the supv bit are accessible in supervisor data space only. mm ?module mapping 0 = internal modules are addressed from $7ff000 ?$7fffff. 1 = internal modules are addressed from $fff000 ?$ffffff. iarb[3:0] ?interrupt arbitration field each module that can generate interrupt requests has an interrupt arbitration (iarb) field. arbitration between interrupt requests of the same priority is performed by serial contention between iarb field bit values. contention must take place whenever an interrupt request is acknowledged, even when there is only a single pending request. an iarb field must have a non-zero value for contention to take place. if an interrupt request from a module with an iarb field value of %0000 is recognized, the cpu pro- cesses a spurious interrupt exception. because the siml routes external interrupt requests to the cpu, the siml iarb field value is used for arbitration between internal and external interrupts of the same priority. the reset value of iarb for the siml is %1111, and the reset value of iarb for all other mod- ules is %0000, which prevents siml interrupts from being discarded during initialization. table 8 show cycle enable bits shen action 00 show cycles disabled, external bus arbitration allowed 01 show cycles enabled, external bus arbitration not allowed 10 show cycles enabled, external bus arbitration allowed 11 show cycles enabled, external bus arbitration allowed, internal activity is halted by a bus grant
motorola mc68ck338 16 MC68CK338TS/d 3.3 system clock the system clock in the siml provides timing signals for the imb modules and for an external peripheral bus. because the mcu is a fully static design, register and memory contents are not affected when the clock rate changes. system hardware and software support changes in clock rate during operation. the system clock signal can be generated in one of two ways. an internal phase-locked loop can synthesize the clock from a reference frequency, or the clock signal can be input directly from an external source. keep these clock sources in mind while reading the rest of this section. figure 5 is a block diagram of the system clock. figure 5 system clock block diagram 3.3.1 clock sources the state of the clock mode (modclk) pin during reset determines the system clock source. when modclk is held high during reset, the clock synthesizer generates a clock signal from a reference frequency connected to the extal pin. the clock synthesizer control register (syncr) determines operating frequency and mode of operation. when modclk is held low during reset, the clock synthesizer is disabled and an external system clock signal must be applied. the syncr control bits have no effect. the input clock is referred to as ? ref ? and can be either a crystal or an external clock source. the output of the clock system is referred to as ? sys ? ensure that f ref and f sys are within normal operating limits. the reference frequency for this mcu is typically 32.768 khz, but can range from 25 khz to 50 khz. to generate a reference frequency using the crystal oscillator, a reference crystal must be connected be- tween the extal and xtal pins. figure 6 shows a recommended circuit. 16/32 pll block phase comparator low-pass filter vco crystal oscillator system clock system clock control feedback divider w x y extal xtal xfc clkout modclk v ddsyn
mc68ck338 motorola MC68CK338TS/d 17 figure 6 system clock oscillator circuit when an external system clock signal is applied (pll disabled, modclk = 0 during reset), the duty cycle of the input is critical, especially at operating frequencies close to maximum. the relationship be- tween clock signal duty cycle and clock signal period is expressed: when the system clock signal is applied directly to the extal pin (pll is disabled, modclk = 0 during reset), or the clock synthesizer reference frequency is supplied by a source other than a crystal (pll enabled, modclk = 1 during reset), the xtal pin must be left floating. in either case, the frequency of the signal applied to extal may not exceed the maximum system clock frequency (pll disabled) or the maximum clock synthesizer reference frequency (pll enabled). 3.3.2 clock synthesizer operation v ddsyn is used to power the clock circuits when the phase-locked loop is used. a separate power source increases mcu noise immunity and can be used to run the clock when the mcu is powered down. a quiet power supply must be used as the v ddsyn source. adequate external bypass capacitors should be placed as close as possible to the v ddsyn pin to assure stable operating frequency. when an external system clock signal is applied and the pll is disabled, v ddsyn should be connected to the v dd supply. refer to the sim reference manual (simrm/ad) for more information regarding system clock power supply conditioning. a voltage controlled oscillator (vco) generates the system clock signal. to maintain a 50% clock duty cycle, the vco frequency (f vco ) is either two or four times the system clock frequency, depending on the state of the x bit in syncr. a portion of the clock signal is fed back to a divider/counter. the divider controls the frequency of one input to a phase comparator. the other phase comparator input is the reference signal connected to the extal pin. the comparator generates a control signal proportional to the difference in phase between the two inputs. the signal is low-pass filtered and used to correct the vco output frequency. filter circuit implementation can vary, depending upon the external environment and required clock sta- bility. figure 7 shows a recommended system clock filter network. xfc pin leakage must be kept within specified limits to maintain optimum stability and pll performance. an external filter network connected to the xfc pin is not required when an external system clock signal is applied and the pll is disabled. the xfc pin must be left floating in this case. 338 oscillator extal xtal 10m w * 4.7 k w * 22 pf * 22 pf * v ssi resistance and capacitance based on a test circuit constructed with a daishinku dmx-38 32.768 khz crystal. specific components must be based on crystal type. contact crystal vendor for exact circuit. * r1 c1 c2 r2 minimum external clock period minimum external clock high/low time 50 % percentage variation of external clock input duty cycle ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ =
motorola mc68ck338 18 MC68CK338TS/d figure 7 system clock filter network when the clock synthesizer is used, syncr determines the operating frequency of the mcu. the fol- lowing equation relates the mcu operating frequency to the clock synthesizer reference frequency (f ref ) and the w, x, and y fields in the syncr: the w bit controls a prescaler tap in the feedback divider. setting w increases vco speed by a factor of four. the y field determines the count modulus for a modulo 64 downcounter, causing it to divide by a value of y+1. when w or y changes, vco frequency (f vco ) changes, and the vco must relock. the x bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. when x=0 (reset state), the divider is enabled, and the system clock is one-fourth the vco frequency. setting x=1 disables the divider, doubling the clock speed without changing the vco frequency. there is no relock delay when clock speed is changed by the x bit. internal vco frequency is determined by the following equations: or for the mcu to operate correctly, system clock and vco frequencies selected by the w, x, and y bits must be within the limits specified for the mcu. do not use a combination of bit values that selects either an operating frequency or a vco frequency greater than the maximum specified values. 3.3.3 clock synthesizer control the clock synthesizer control circuits determine system clock frequency and clock operation under spe- cial circumstances, such as following loss of synthesizer reference or during low-power operation. clock source is determined by the logic state of the modclk pin during reset. notes: 1. ensure that initialization software does not change the value of this bit (it should always be zero). syncr clock synthesizer control register $yffa04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w x y ediv stcpu 0 rsvd 1 slock rsvd 1 stsim stext reset: 0 0 1 1 1 1 1 1 0 0 0 0 u 0 0 0 32 xfc conn * maintain low leakage on the xfc node. 0.01 m f 0.1 m f xfc * 0.1 m f c4 c3 c1 v ddsyn v ddsyn v ssi f sys 4f ref y1 + () 2 2w x + () = f vco 4f sys if x = 0 = f vco 2f sys if x = 1 =
mc68ck338 motorola MC68CK338TS/d 19 when the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of syncr. bits in the lower byte show the status of or control the operation of internal and external clocks. syncr can be read or written only when the cpu is operating in supervisor mode. w ?frequency control (vco) this bit controls a prescaler tap in the synthesizer feedback loop. setting it increases the vco speed by a factor of four. vco relock delay is required. x ?frequency control (prescaler) this bit controls a divide by two prescaler that is not in the synthesizer feedback loop. setting it doubles the clock speed without changing the vco speed. no vco relock delay is required. y[5:0] ?frequency control (counter) the y field controls the modulus down counter in the synthesizer feedback loop, causing it to divide by a value of y + 1. values range from 0 to 63. vco relock delay is required. ediv ?e clock divide rate 0 = eclk frequency is system clock divided by 8. 1 = eclk frequency is system clock divided by 16. eclk is an external m6800 bus clock available on pin addr23. refer to 3.6 chip-selects for more information. stcpu ?stop cpu32l clock on lpstop 0 = when lpstop is executed, the intermodule bus clock (imbclk) is held low. when a trace, reset exception, or siml interrupt occurs, the imbclk turns back on and the cpu32l begins executing instructions again. 1 = when lpstop is executed, the imbclk continues to run but is gated off and held low only where it enters the cpu32l. when a trace, reset exception, or interrupt from any module oc- curs, the imbclk is gated back on where it enters the cpu32l, and execution begins again. slock ?synthesizer lock flag 0 = vco has not locked, but is enabled on the desired frequency. 1 = vco has locked on the desired frequency, or is disabled. the mcu remains in reset until the synthesizer locks, but slock does not indicate synthesizer lock status until after the user writes to syncr. stsim ?stop mode siml clock 0 = when lpstop is executed, the siml clock is driven by the crystal oscillator and the vco is turned off to conserve power. 1 = when lpstop is executed, the siml clock is driven by the vco. stext ?stop mode external clock 0 = when lpstop is executed, the clkout signal is held negated to conserve power. 1 = when lpstop is executed, the clkout signal is driven by the siml clock, as determined by the state of the stsim bit. 3.3.4 external mc6800 bus clock the state of the eclk division rate bit (ediv) in syncr determines clock rate for the eclk signal avail- able on pin addr23. eclk is a bus clock for mc6800 devices and peripherals. eclk frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen. the clock is enabled by the cs10 field in chip-select pin assignment register 1 (cspar1). eclk operation during low-power stop is described in the following paragraph. refer to 3.6 chip-selects for more in- formation about the external bus clock.
motorola mc68ck338 20 MC68CK338TS/d 3.3.5 low-power operation low-power operation is initiated by the cpu32l. to reduce power consumption selectively, the cpu32l can enter the following low-power modes: 1. the cpu32l can selectively disable a module by setting the module? stop bit. 2. the cpu32l can execute the stop instruction. 3. the cpu32l can execute the lpstop instruction to stop the operations of only the cpu32l or the entire mcu, including the cpu32l. if the stop bit in a module is set, then that module enters a low power mode. some or all of that mod- ule? registers remain accessible. the module can be restarted by asserting reset or by the cpu32l clearing the module? stop bit. the cpu32l can enter a low power mode by executing the stop instruction. it can be reawakened by reset , trace or interrupt. 3.3.5.1 normal lpstop mode this low-power stop mode offers the greatest power reduction. to enter normal lpstop mode, the cpu32l executes the lpstop instruction after clearing the stcpu bit in syncr. this causes the siml to turn off the system clock to most of the mcu. when the cpu executes lpstop, a special cpu space bus cycle writes a copy of the current interrupt mask into the clock control logic. the siml brings the mcu out of normal lpstop mode when one of the following exceptions occurs: ?reset ?trace ?siml interrupt of higher priority than the stored interrupt mask during a lpstop, unless the system clock signal is supplied by an external source and that source is removed, the siml clock control logic and the siml clock signal (simclk) continue to operate. the periodic interrupt timer and input logic for the reset and irq pins are clocked by simclk, and can be used to bring the processor out of lpstop. the software watchdog monitor cannot perform this function. optionally, the siml can also continue to generate the clkout signal while in lpstop. stsim and stext bits in syncr determine clock operation during lpstop. 3.3.5.2 modified lpstop mode to enter modified lpstop mode, the cpu32l first sets the stcpu bit in syncr, then executes the lpstop instruction. this causes the siml to turn off the system clock to the cpu32l only. the other mcu modules continue to operate. the siml brings the mcu out of normal lpstop mode when one of the following exceptions occurs: ?reset ?trace ?interrupt of higher priority than the stored interrupt mask from any mcu module this low-power stop mode offers better power reduction than using the stop instruction since the clock in the cpu32l is held inactive. also, the stop bits of individual modules may be set or cleared, leaving some active and others inactive. the flow chart shown in figure 8 summarizes the effects of the stcpu, stsim, and stext bits when the mcu enters normal or modified lpstop mode. note to keep power consumption to a minimum when in lpstop mode, do not allow any spurious interrupts to occur. if a spurious interrupt occurs during lpstop mode, the device will transition to the stop mode (which has greater power consumption) until a non-spurious interrupt request is detected by the cpu32l.
mc68ck338 motorola MC68CK338TS/d 21 figure 8 lpstop flowchart setup interrupt to wake up mcu from lpstop leave imbclk 1 on in lpstop? no yes set stop bits for modules that will not be active in lpstop set stcpu 2 = 1 f imbclk = f sys in lpstop set stcpu 2 = 0 f imbclk = 0 hz in lpstop using external clock? no yes use system clock as simclk in lpstop? no yes set stsim = 1 f simclk 3 = f sys in lpstop want clkout on in lpstop? no yes no yes want clkout on in lpstop? set stsim = 0 f simclk 3 = f ref in lpstop set stext = 1 f clkout 4 = f sys f eclk = ? f sys in lpstop set stext = 0 f clkout 4 = 0 hz f eclk = ? 0 hz in lpstop set stext = 1 f clkout 4 = f ref f eclk = ? 0 hz in lpstop set stext = 0 f clkout 4 = 0 hz f eclk = ? 0 hz in lpstop enter lpstop notes: 1. imbclk is the clock used by the cpu32l, qsm, ctm6, and the siml. 2. when stcpu = 1, the cpu32l is shutdown in lpstop. all other modules will remain active unless the stop bits in their module configuration registers are set prior to entering lpstop. 3. the simclk is used by the pit, irq , and input blocks of the siml. 4. clkout control during lpstop is overridden by the exoff bit in simlcr. if exoff = 1, the clkout pin is always in a high impedance state and stext has no effect in lpstop. if exoff = 0, clkout is controlled by stext in lpstop. when stcpu = 1, the cpu32l is disabled in lpstop, but all other modules remain active or stopped according to the setting. lpstop flowchart
motorola mc68ck338 22 MC68CK338TS/d 3.4 system protection block system protection includes a bus monitor, a halt monitor, a spurious interrupt monitor, and a software watchdog timer. these functions reduce the number of external components required for complete sys- tem control. figure 9 shows the system protection block. figure 9 system protection block 3.4.1 system protection control register the system protection control register controls the software watchdog timer, bus monitor, and halt monitor. this register can be written only once following power-on or reset, but can be read at any time. swe ?software watchdog enable 0 = software watchdog disabled 1 = software watchdog enabled sypcr system protection control register $yffa21 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used swe swp swt[1:0] hme bme bmt reset: 1 modclk 0 0 0 0 0 0 sys protect block module configuration and test reset status halt monitor bus monitor spurious interrupt monitor software watchdog timer periodic interrupt timer 2 9 prescaler clock irq[7:1] berr reset request reset request
mc68ck338 motorola MC68CK338TS/d 23 swp ?software watchdog prescaler this bit controls the value of the software watchdog prescaler. 0 = software watchdog clock not prescaled 1 = software watchdog clock prescaled by 512 swt[1:0] ?software watchdog timing this field selects the divide ratio used to establish software watchdog time-out period. table 9 gives the ratio for each combination of swp and swt bits. hme ?halt monitor enable 0 = disable halt monitor function 1 = enable halt monitor function bme ?bus monitor enable 0 = disable bus monitor function for internal to external bus cycles. 1 = enable bus monitor function for internal to external bus cycles. bmt[1:0] ?bus monitor timing this bit field selects the time-out period in system clocks for the bus monitor. refer to table 10 . 3.4.2 bus monitor the internal bus monitor checks for excessively long dsa ck response times during normal bus cycles and for excessively long dsa ck or a vec response times during interrupt acknowledge (iack) cycles. the monitor asserts berr if the response time exceeds a user-specified time-out period. dsa ck and a vec response times are measured in clock cycles. the maximum allowable response time can be selected by setting the bmt[1:0] field. table 9 software watchdog timing field swp swt[1:0] watchdog time-out period 000 2 9 ? f sys 001 2 11 ? f sys 010 2 13 ? f sys 011 2 15 ? f sys 100 2 18 ? f sys 101 2 20 ? f sys 110 2 22 ? f sys 111 2 24 ? f sys table 10 bus monitor time-out period bmt[1:0] bus monitor time-out period 00 64 system clocks 01 32 system clocks 10 16 system clocks 11 8 system clocks
motorola mc68ck338 24 MC68CK338TS/d the monitor does not check dsa ck response on the external bus unless the cpu initiates the bus cy- cle. the bme bit in sypcr enables the internal bus monitor for internal to external bus cycles. if a sys- tem contains external bus masters, an external bus monitor must be implemented and the internal to external bus monitor option must be disabled. 3.4.3 halt monitor the halt monitor responds to assertion of the hal t signal on the internal bus caused by a double bus fault. a double bus fault occurs when: ?bus error exception processing begins and a second berr is detected before the first instruction of the first exception handler is executed. ?one or more bus errors occur before the first instruction after a reset exception is executed. ?a bus error occurs while the cpu is loading information from a bus error stack frame during a re- turn from exception (rte) instruction. if the halt monitor is enabled by setting hme in sypcr, the mcu will issue a reset when a double bus fault occurs, otherwise the mcu will remain halted. a flag in the reset status register (rsr) indicates that the last reset was caused by the halt monitor. 3.4.4 spurious interrupt monitor the spurious interrupt monitor issues berr if no interrupt arbitration occurs during an interrupt ac- knowledge cycle. leaving iarb[3:0] set to %0000 in the module configuration register of any peripheral that can generate interrupts will cause a spurious interrupt. 3.4.5 software watchdog the software watchdog is controlled by swe in sypcr. once enabled, the watchdog requires that a service sequence be written to swsr on a periodic basis. if servicing does not take place, the watchdog times out and issues a reset. this register can be written at any time, but returns zeros when read. each time the service sequence is written, the software watchdog timer restarts. the servicing se- quence consists of the following steps: 1. write $55 to swsr. 2. write $aa to swsr. both writes must occur before time-out in the order listed, but any number of instructions can be exe- cuted between the two writes. the watchdog clock rate is affected by swp and swt[1:0] in sypcr. when swt[1:0] are modified, a watchdog service sequence must be performed before the new time-out period takes effect. the reset value of swp is affected by the state of the modclk pin on the rising edge of reset . refer to table 11 . swsr software service register $yffa27 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used swsr reset: 0 0 0 0 0 0 0 0
mc68ck338 motorola MC68CK338TS/d 25 3.4.6 periodic interrupt timer the periodic interrupt timer (pit) generates interrupts at user-programmable intervals. timing for the pit is provided by a programmable prescaler driven by the system clock. this register contains information concerning periodic interrupt priority and vectoring. bits [10:0] can be read or written at any time. bits [15:11] are unimplemented and always return zero. pirql[2:0] ?periodic interrupt request level table 12 shows what interrupt request level is asserted when a periodic interrupt is generated. if a pit interrupt and an external irq signal of the same priority occur simultaneously, the pit interrupt is ser- viced first. the periodic timer continues to run when the interrupt is disabled. piv[7:0] ?periodic interrupt vector this bit field contains the vector generated in response to an interrupt from the periodic timer. when the siml responds, the periodic interrupt vector is placed on the bus. pitr contains the count value for the periodic timer. setting the pitm[7:0] field turns off the periodic timer. this register can be read or written at any time. table 11 modclk pin states modclk swp 01 10 picr periodic interrupt control register $yffa22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 pirql[2:0] piv[7:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 table 12 periodic interrupt request levels pirql[2:0] interrupt request level 000 periodic interrupt disabled 001 interrupt request level 1 010 interrupt request level 2 011 interrupt request level 3 100 interrupt request level 4 101 interrupt request level 5 110 interrupt request level 6 111 interrupt request level 7 pitr periodic interrupt timer register $yffa24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 ptp pitm[7:0] reset: 0 0 0 0 0 0 0 modclk 0 0 0 0 0 0 0 0
motorola mc68ck338 26 MC68CK338TS/d ptp ?periodic timer prescaler control 0 = periodic timer clock not prescaled 1 = periodic timer clock prescaled by 512 the reset state of ptp is the complement of the state of the modclk signal at the rising edge of re set . pitm[7:0] ?periodic interrupt timer modulus this is an 8-bit timing modulus. the period of the timer can be calculated as follows: where pit period = periodic interrupt timer period pitm[7:0] = periodic interrupt timer register modulus f ref = synthesizer reference of external clock input frequency prescaler = 1 if ptp = 0 or 512 if ptp = 1 3.5 external bus interface the external bus interface (ebi) transfers information between the internal mcu bus and external de- vices. the external bus has 24 address lines and 16 data lines. the ebi provides dynamic sizing between 8-bit and 16-bit data accesses. it supports byte, word, and long-word transfers. ports are accessed through the use of asynchronous cycles controlled by the size (siz1 and siz0) and data size acknowledge (dsa ck1 and dsa ck0 ) pins. multiple bus cycles may be required for dynamically sized transfer. port width is the maximum number of bits accepted or provided during a bus transfer. external devices must follow the handshake protocol described below. control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. the selected device controls the length of the cycle. strobe signals, one for the address bus and another for the data bus, indicate the validity of an address and provide timing information for data. the ebi operates in an asynchronous mode for any port width. to add flexibility and minimize the necessity for external logic, mcu chip-select logic can be synchro- nized with ebi transfers. chip-select logic can also provide internally-generated bus control signals for these accesses. refer to 3.6 chip-selects for more information. 3.5.1 bus control signals the cpu initiates a bus cycle by driving the address, size, function code, and read/write outputs. at the beginning of the cycle, size signals siz0 and siz1 are driven along with the function code signals (fc[2:0]). the size signals indicate the number of bytes remaining to be transferred during an operand cycle. they are valid while the address strobe as is asserted. table 13 shows siz0 and siz1 encoding. the read/write (r/w ) signal determines the direction of the transfer during a bus cycle. this signal changes state, when required, at the beginning of a bus cycle, and is valid while as is asserted. the r/w signal only changes state when a write cycle is preceded by a read cycle or vice versa. the signal can remain low for two consecutive write cycles. pit period 4 pitm[7:0] () prescaler () f ref ---------------------------------------------------------------- - =
mc68ck338 motorola MC68CK338TS/d 27 3.5.2 function codes the cpu32l automatically generates function code signals fc[2:0]. the function codes can be consid- ered address extensions that automatically select one of eight address spaces to which an address ap- plies. these spaces are designated as either user or supervisor, and program or data spaces. address space seven is designated cpu space. cpu space is used for control information not normally associ- ated with read or write bus cycles. function codes are valid while as is asserted. table 14 displays cpu32l address space encodings. 3.5.3 address bus address bus signals addr[23:0] define the address of the most significant byte to be transferred during a bus cycle. the mcu places the address on the bus at the beginning of a bus cycle. the address is valid while as is asserted. 3.5.4 address strobe as is a timing signal that indicates the validity of an address on the address bus and the validity of many control signals. it is asserted one-half clock after the beginning of a bus cycle. 3.5.5 data bus data bus signals data[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data to or from the mcu. a read or write operation can transfer 8 or 16 bits of data in one bus cycle. during a read cycle, the data is latched by the mcu on the last falling edge of the clock for that bus cycle. for a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. the mcu places the data on the data bus one-half clock cycle after as is asserted in a write cycle. table 13 size signal encoding siz1 siz0 transfer size 0 1 byte 1 0 word 1 1 three byte 0 0 long word table 14 cpu32l address space encoding fc2 fc1 fc0 address space 0 0 0 reserved 0 0 1 user data space 0 1 0 user program space 0 1 1 reserved 1 0 0 reserved 1 0 1 supervisor data space 1 1 0 supervisor program space 1 1 1 cpu space
motorola mc68ck338 28 MC68CK338TS/d 3.5.6 data strobe data strobe (ds ) is a timing signal. for a read cycle, the mcu asserts ds to signal an external device to place data on the bus. ds is asserted at the same time as as during a read cycle. for a write cycle, ds signals an external device that data on the bus is valid. the mcu asserts ds one full clock cycle after the assertion of as during a write cycle. 3.5.7 bus cycle termination signals during bus cycles, external devices assert the data size acknowledge signals dsa ck1 and dsa ck0 . during a read cycle, the signals tell the mcu to terminate the bus cycle and to latch data. during a write cycle, the signals indicate that an external device has successfully stored data and that the cycle can end. these signals also indicate to the mcu the size of the port for the bus cycle just completed. alter- nately, chip-selects can be used to generate dsa ck1 and dsa ck0 internally. refer to 3.5.8 dynamic bus sizing for more information. the bus error (berr ) signal is also a bus cycle termination indicator and can be used in the absence of dsa ck1 and dsa ck0 to indicate a bus error condition. it can also be asserted in conjunction with these signals, provided it meets the appropriate timing requirements. the internal bus monitor can be used to generate the berr signal for internal-to-external transfers. when berr and hal t are assert- ed simultaneously, the cpu takes a bus error exception. the autovector signal (a vec ) can terminate irq pin interrupt acknowledge cycles. a vec indicates that the mcu will internally generate a vector number to locate an interrupt handler routine. if it is continu- ously asserted, autovectors will be generated for all external interrupt requests. a vec is ignored during all other bus cycles. 3.5.8 dynamic bus sizing the mcu dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. during an operand transfer cycle, the slave device sig- nals its port size and indicates completion of the bus cycle to the mcu through the use of the dsa ck1 and dsa ck0 inputs, as shown in table 15 . for example, if the mcu is executing an instruction that reads a long-word operand from a 16-bit port, the mcu latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. the operation for an 8-bit port is similar, but requires four read cycles. the addressed device uses the dsa ck0 and dsa ck1 signals to indicate the port width. for instance, a 16-bit device always returns dsa ck0 = 1 and dsa ck1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word operation. dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. a 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data bus bits [15:8]. this minimizes the number of bus cycles needed to transfer data and ensures that the mcu transfers valid data. table 15 effect of dsa ck signals dsa ck1 dsa ck0 result 1 1 insert wait states in current bus cycle 1 0 complete cycle ?data bus port size is 8 bits 0 1 complete cycle ?data bus port size is 16 bits 0 0 reserved
mc68ck338 motorola MC68CK338TS/d 29 the mcu always attempts to transfer the maximum amount of data on all bus cycles. for a word oper- ation, it is assumed that the port is 16 bits wide when the bus cycle begins. operand bytes are desig- nated as shown in figure 10 . op0 is the most significant byte of a long-word operand, and op3 is the least significant byte. the two bytes of a word-length operand are op0 (most significant) and op1. the single byte of a byte-length operand is op0. figure 10 operand byte order 3.5.9 operand alignment the data multiplexer establishes the necessary connections for different combinations of address and data sizes. the multiplexer takes the two bytes of the 16-bit bus and routes them to their required po- sitions. positioning of bytes is determined by the size and address outputs. siz1 and siz0 indicate the remaining number of bytes to be transferred during the current bus cycle. the number of bytes trans- ferred is equal to or less than the size indicated by siz1 and siz0, depending on port width. addr0 also affects the operation of the data multiplexer. during an operand transfer, addr[23:1] indicate the word base address of the portion of the operand to be accessed, and addr0 indicates the byte offset from the base. 3.5.10 misaligned operands cpu32l processor architecture uses a basic operand size of 16 bits. an operand is misaligned when it overlaps a word boundary. this is determined by the value of addr0. when addr0 = 0 (an even ad- dress), the address is on a word and byte boundary. when addr0 = 1 (an odd address), the address is on a byte boundary only. a byte operand is aligned at any address; a word or long-word operand is misaligned at an odd address. the cpu32l does not support misaligned operand transfers, and gives an address error exception if one is attempted. the largest amount of data that can be transferred by a single bus cycle is an aligned word. if the mcu transfers a long-word operand via a 16-bit port, the most significant operand word is transferred on the first bus cycle and the least significant operand word on a following bus cycle. 3.5.11 operand transfer cases table 16 summarizes how operands are aligned for various types of transfers. opn entries are portions of a requested operand that are read or written during a bus cycle and are defined by siz1, siz0, and addr0 for that bus cycle. op0 operand byte order op1 op2 op3 24 31 23 16 15 8 7 0 byte order operand long word three byte word byte op2 op1 op0 op1 op0 op0
motorola mc68ck338 30 MC68CK338TS/d 3.6 chip-selects typical microcontrollers require additional hardware to provide external chip-select and address de- code signals. the mc68338 includes 12 programmable chip-selects that can provide 2 to 16-clock-cy- cle access to external memory and peripherals. address block sizes of two kbytes to one mbyte can be selected. figure 11 is a functional diagram of a chip-select circuit. chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobe, or interrupt acknowledge signals. chip-select logic can also generate dsa ck and a vec signals internally. each signal can also be synchronized with the eclk signal available on addr23. figure 11 chip-select circuit block diagram notes: 1. all transfers are aligned. the cpu32l does not support misaligned word or long-word transfers. 2. operands in parentheses are ignored by the cpu32l during read cycles. 3. 3-byte transfer cases occur only as a result of a long word to 8-bit port transfer. table 16 operand alignment current cycle transfer case 1 siz1 siz0 addr0 dsa ck1 dsa ck0 data [15:8] data [7:0] next cycle 1 byte to 8-bit port (even) 0 1 0 1 0 op0 (op0) 2 2 byte to 8-bit port (odd) 0 1 1 1 0 op0 (op0) 3 byte to 16-bit port (even) 0 1 0 0 1 op0 (op0) 4 byte to 16-bit port (odd) 0 1 1 0 1 (op0) op0 5 word to 8-bit port 1 0 0 1 0 op0 (op1) 2 6 word to 16-bit port 1 0 0 0 1 op0 op1 7 3-byte to 8-bit port 3 1 1 1 1 0 op0 (op0) 5 8 long word to 8-bit port 0 0 0 1 0 op0 (op0) 7 9 long word to 16-bit port 0 0 0 0 1 op0 op1 6 chip sel block avec generator dsack generator pin assignment register pin data register base address register timing and control address comparator option compare option register avec dsack pin bus control internal signals address
mc68ck338 motorola MC68CK338TS/d 31 when a memory access occurs, chip-select logic compares address space type, address, type of ac- cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in chip-select registers. if all parameters match, the appropriate chip-select signal is asserted. select sig- nals are active low. if a chip-select function is given the same address as a microcontroller module or an internal memory array, an access to that address goes to the module or array, and the chip-select signal is not asserted. the external address and data buses do not reflect the internal access. all chip-select circuits except csboo t are disabled out of reset. chip-select option registers must not be written until base addresses have been written to the proper base address registers. alternate func- tions for chip-select pins are enabled if appropriate data bus pins are held low at the release of reset . table 17 lists allocation of chip-selects and discrete outputs on the pins of the mcu. 3.6.1 chip-select registers each chip-select pin can have one or more functions. chip-select pin assignment registers cspar[0:1] determine functions of the pins. pin assignment registers also determine port size for dynamic bus al- location. a pin data register (portc) latches data for chip-select pins that are used for discrete output. blocks of addresses are assigned to each chip-select function. block sizes of two kbytes to one mbyte can be selected by writing values to the appropriate base address registers csbarbt and cs- bar[0:10]. multiple chip-selects assigned to the same block of addresses must have the same number of wait states. chip-select option registers csorbt and csor[0:10] determine timing of and conditions for assertion of chip-select signals. eight parameters, including operating mode, access size, synchronization, and wait state insertion can be specified. initialization software usually resides in a peripheral memory device controlled by the chip-select cir- cuits. csboo t and registers csorbt and csbarbt are provided to support bootstrap operation. 3.6.2 pin assignment registers the pin assignment registers contain twelve 2-bit fields that determine functions of the chip-select pins. each pin has two or three possible functions, as shown in table 18 . table 17 chip-select and discrete output allocation pin chip-select discrete outputs csboo t csboo t ? br cs0 ? bg cs1 ? bga ck cs2 ? fc0 cs3 pc0 fc1 cs4 pc1 fc2 cs5 pc2 addr19 cs6 pc3 addr20 cs7 pc4 addr21 cs8 pc5 addr22 cs9 pc6 addr23 cs10
motorola mc68ck338 32 MC68CK338TS/d table 19 shows pin assignment field encoding. pins that have no discrete output function do not use the %00 encoding. cspar0 contains seven 2-bit fields that determine the functions of corresponding chip-select pins. cspar0[15:14] are not used. these bits always read zero; writes have no effect. cspar0 bit 1 always reads one; writes to cspar0 bit 1 have no effect. table 20 shows cspar0 pin assignments. table 18 chip-select pin functions assignment register 16-bit chip-select alternate function discrete output cspar0 csboo t csboo t ? cs0 br ? cs1 bg ? cs2 bga ck ? cs3 fc0 pc0 cs4 fc1 pc1 cs5 fc2 pc2 cspar1 cs6 addr19 pc3 cs7 addr20 pc4 cs8 addr21 pc5 cs9 addr22 pc6 cs10 addr23 eclk table 19 pin assignment encodings bit field description 00 discrete output 01 alternate function 10 chip-select (8-bit port) 11 chip-select (16-bit port) cspar0 chip-select pin assignment register 0 $yffa44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 cs5pa[1:0] cs4pa[1:0] cs3pa[1:0] cs2pa[1:0] cs1pa[1:0] cs0pa[1:0] csbtpa[1:0] reset: 0 0 data2 1 data2 1 data2 1 data1 1 data1 1 data1 1 1 data0
mc68ck338 motorola MC68CK338TS/d 33 the reset state of data[7:3] determines whether pins controlled by cspar1 are initially configured as high-order address lines or chip-selects. table 21 shows the correspondence between data[7:3] and the reset configuration of cs[10:6] /addr[23:19]. cspar1 contains five 2-bit fields that determine the functions of corresponding chip-select pins. cspar1[15:10] are not used. these bits always read zero; writes have no effect. table 22 shows cspar1 pin assignments. notes: 1. refer to table 21 for cspar1 reset state information. table 20 cspar0 pin assignments cspar0 field chip-select signal alternate signal discrete output cs5pa[1:0] cs5 fc2 pc2 cs4pa[1:0] cs4 fc1 pc1 cs3pa[1:0] cs3 fc0 pc0 cs2pa[1:0] cs2 bga ck cs1pa[1:0] cs1 bg cs0pa[1:0] cs0 br csbtpa[1:0] csboo t cspar1 chip-select pin assignment register 1 $yffa46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cs10pa[1:0] cs9pa[1:0] cs8pa[1:0] cs7pa[1:0] cs6pa[1:0] reset: 0 0 0 0 0 0 data7 1 1 data [7:6] 1 1 data [7:5] 1 1 data [7:4] 1 1 data [7:3] 1 1 table 21 reset pin function of cs[10:6] data bus pins at reset chip-select/address bus pin function data7 data6 data5 data4 data3 cs10 / addr23 cs9 / addr22 cs8 / addr21 cs7 / addr20 cs8 / addr19 11111 cs10 cs9 cs8 cs7 cs6 1111 0 cs10 cs9 cs8 cs7 addr19 111 0 x cs10 cs9 cs8 addr20 addr19 11 0 x x cs10 cs9 addr21 addr20 addr19 1 0 x x x cs10 addr22 addr21 addr20 addr19 0xxxx addr23 addr22 addr21 addr20 addr19
motorola mc68ck338 34 MC68CK338TS/d port size determines the way in which bus transfers to external addresses are allocated. port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip-select. port size and transfer size affect how the chip-select signal is asserted. refer to 3.6.4 option registers for more information. out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin. these pins have weak internal pull-up drivers, but can be held low by external devices. either 16-bit chip-select function (%11) or alternate function (%01) can be selected during reset. all pins except the boot rom select pin (csboo t ) are disabled out of reset. the csboo t signal is normally enabled out of reset. the state of the data0 line during reset deter- mines what port width csboo t uses. if data0 is held high (either by the weak internal pull-up driver or by an external pull-up device), 16-bit width is selected. if data0 is held low, 8-bit port size is selected. a pin programmed as a discrete output drives an external signal to the value specified in the pin data register. no discrete output function is available on pins csboo t , br , bg , or bga ck . addr23 pro- vides eclk output rather than a discrete output signal. when a pin is programmed for discrete output or alternate function, internal chip-select logic still func- tions and can be used to generate dsa ck or a vec internally on an address and control signal match. 3.6.3 base address registers each chip-select has an associated base address register. a base address is the lowest address in the block of addresses enabled by a chip-select. block size is the extent of the address block above the base address. block size is determined by the value contained in a blksz field. multiple chip-selects may be assigned to the same block of addresses so long as each chip-select uses the same number of wait states. the blksz field determines which bits in the base address field are compared to corresponding bits on the address bus during an access. provided other constraints determined by option register fields are also satisfied, when a match occurs, the associated chip-select signal is asserted. after reset, the mcu fetches the address of the first instruction to be executed from the reset vector, located beginning at address $000000 in program space. to support bootstrap operation from reset, the base address field in csbarbt has a reset value of all zeros. a memory device containing the reset vector and an initialization routine can be automatically enabled by csboo t after a reset. the block size field in csbarbt has a reset value of one mbyte. table 22 cspar1 pin assignments cspar1 field chip-select signal alternate signal discrete output cs10pa[1:0] cs10 addr23 eclk cs9pa[1:0] cs9 addr22 pc6 cs8pa[1:0] cs8 addr21 pc5 cs7pa[1:0] cs7 addr20 pc4 cs6pa[1:0] cs6 addr19 pc3 csbarbt chip-select base address register boot rom $yffa48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz[2:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
mc68ck338 motorola MC68CK338TS/d 35 addr[23:11] ?base address field this field sets the starting address of a particular chip-select? address space. the address compare logic uses only the most significant bits to match an address within a block. the value of the base ad- dress must be a multiple of the block size. the base address register diagrams above show how register bits correspond to cpu address lines. blksz[2:0] ?block size field this field determines the size of the block that must be enabled by the chip-select. table 23 shows bit encoding for the base address registers block size field. 3.6.4 option registers the option registers contain eight fields that determine timing of and conditions for assertion of chip- select signals. to assert a chip-select signal, and to provide dsa ck or autovector support, other con- straints set by fields in the option register and in the base address register must also be satisfied. csbar[0:10] chip-select base address registers $yffa4c?yffa74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 addr 23 addr 22 addr 21 addr 20 addr 19 addr 18 addr 17 addr 16 addr 15 addr 14 addr 13 addr 12 addr 11 blksz[2:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 23 block size field bit encoding block size field block size address lines compared 000 2 kbyte addr[23:11] 001 8 kbyte addr[23:13] 010 16 kbyte addr[23:14] 011 64 kbyte addr[23:16] 100 128 kbyte addr[23:17] 101 256 kbyte addr[23:18] 110 512 kbyte addr[23:19] 111 1 mbyte addr[23:20] csorbt chip-select option register boot rom $yffa4a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode byte[1:0] r/ w [1:0] strb dsa ck[3:0] space[1:0] ipl[2:0] a vec reset: 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 csor[0:10] chip-select option registers $yffa4e?ffa76 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode byte[1:0] r/ w [1:0] strb dsa ck[3:0] space[1:0] ipl[2:0] a vec reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola mc68ck338 36 MC68CK338TS/d csorbt, the option register for csboo t , contains special reset values that support bootstrap opera- tion from peripheral memory devices. the following bit descriptions apply to both csorbt and csor[0:10] option registers. mode ?asynchronous/synchronous mode 0 = asynchronous mode (chip-select assertion determined by bus control signals) 1 = synchronous mode (chip-select assertion synchronized with eclk signal) in asynchronous mode, the chip-select is asserted synchronized with as or ds . dsa ck[3:0] is not used in synchronous mode because a bus cycle is only performed as a synchronous operation. when a match condition occurs on a chip-select programmed for synchronous operation, the chip-select signals the ebi that an eclk cycle is pending. byte[1:0] ?upper/lower byte option this field is used only when the chip-select 16-bit port option is selected in the pin assignment register. table 24 lists upper/lower byte options. r/w [1:0] ?read/write this field causes a chip-select to be asserted only for reads, only for writes, or for both reads and writes. refer to table 25 for options available. strb ?address strobe/data strobe 0 = address strobe 1 = data strobe this bit controls the timing for assertion of a chip-select in asynchronous mode. selecting address strobe causes chip-select to be asserted synchronized with address strobe. selecting data strobe caus- es chip-select to be asserted synchronized with data strobe. dsa ck[3:0] ?data and size acknowledge this field specifies the source of dsa ck[3:0] in asynchronous mode. it also allows the user to adjust bus timing with internal dsa ck[3:0] generation by controlling the number of wait states that are inserted to optimize bus speed in a particular application. table 26 shows the dsa ck[3:0] encoding. the fast termination encoding (%1110) is used for two-cycle access to external memory. table 24 upper/lower byte options byte[1:0] description 00 disable 01 lower byte 10 upper byte 11 both bytes table 25 r/w encodings r/w [1:0] description 00 reserved 01 read only 10 write only 11 read/write
mc68ck338 motorola MC68CK338TS/d 37 space[1:0] ?address space use this option field to select an address space for the chip-select logic. the cpu32l normally operates in supervisor or user space, but interrupt acknowledge cycles must take place in cpu space. table 27 shows address space bit encodings. ipl[2:0] ?interrupt priority level if the space field is set for cpu space, chip-select logic can be used for interrupt acknowledge. during an interrupt acknowledge cycle, the priority level on address lines addr[3:1] is compared to the value in ipl[2:0]. if the values are the same, a chip-select is asserted, provided that other option register con- ditions are met. table 28 shows ipl[2:0] encoding. table 26 dsa ck field encoding dsa ck[3:0] clock cycles required per access wait states per access 0000 3 0 wait states 0001 4 1 wait state 0010 5 2 wait states 0011 6 3 wait states 0100 7 4 wait states 0101 8 5 wait states 0110 9 6 wait states 0111 10 7 wait states 1000 11 8 wait states 1001 12 9 wait states 1010 13 10 wait states 1011 14 11 wait states 1100 15 12 wait states 1101 16 13 wait states 1110 2 fast termination 1111 external dsa ck table 27 address space bit encodings space[1:0] address space 00 cpu space 01 user space 10 supervisor space 11 supervisor/user space
motorola mc68ck338 38 MC68CK338TS/d this field only affects the response of chip-selects and does not affect interrupt recognition by the cpu. any level means that chip-select is asserted regardless of the level of the interrupt acknowledge cycle. a vec ?autovector enable 0 = external interrupt vector enabled 1 = autovector enabled this field selects one of two methods of acquiring an interrupt vector number during an external interrupt acknowledge cycle. if the chip-select is configured to trigger on an interrupt acknowledge cycle (space[1:0] = %00) and the a vec field is set to one, the chip-select circuit generates an internal a vec signal in response to an external interrupt cycle, and the siml supplies an automatic vector number. otherwise, the vector num- ber must be supplied by the requesting device. an internal autovector is generated only in response to interrupt requests from the siml irq pins. interrupt requests from other imb modules are ignored. the a vec bit must not be used in synchronous mode, as autovector response timing can vary because of eclk synchronization. 3.6.5 port c data register bit values in port c determine the state of chip-select pins used for discrete output. when a pin is as- signed as a discrete output, the value in this register appears at the output. this is a read/write register. bit 7 is not used. writing to this bit has no effect, and it always returns zero when read. 3.7 general-purpose input/output siml pins can be configured as two general-purpose i/o ports, e and f. the following paragraphs de- scribe registers that control the ports. table 28 interrupt priority level field encoding ipl[2:0] interrupt priority level 000 any level 001 1 010 2 011 3 100 4 101 5 110 6 111 7 portc port c data register $yffa41 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used 0 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 0 1 1 1 1 1 1 1
mc68ck338 motorola MC68CK338TS/d 39 a write to the port e data register is stored in the internal data latch and, if any port e pin is configured as an output, the value stored for that bit is driven on the pin. a read of the port e data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. the port e data register is a single register that can be accessed in two locations. when accessed at $yffa11, the register is referred to as porte0; when accessed at $yffa13, the register is referred to as porte1. the register can be read or written at any time. it is unaffected by reset. the bits in this register control the direction of the pin drivers when the pins are configured as i/o. any bit in this register set to one configures the corresponding pin as an output. any bit in this register cleared to zero configures the corresponding pin as an input. this register can be read or written at any time. the bits in this register control the function of each port e pin. any bit set to one configures the corre- sponding pin as a bus control signal, with the function shown in table 29 . any bit cleared to zero defines the corresponding pin to be an i/o pin, controlled by porte and ddre. data bus bit 8 controls the state of this register following reset. if data8 is set to one during reset, the register is set to $ff, which defines all port e pins as bus control signals. if data8 is cleared to zero during reset, this register is set to $00, configuring all port e pins as i/o pins. porte0, porte1 port e data register $yffa11, yffa13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: u u u u u u u u ddre port e data direction register $yffa15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 reset: 0 0 0 0 0 0 0 0 pepar port e pin assignment $yffa17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pepa7 pepa6 pepa5 pepa4 pepa3 pepa2 pepa1 pepa0 reset: data8 data8 data8 data8 data8 data8 data8 data8
motorola mc68ck338 40 MC68CK338TS/d the write to the port f data register is stored in the internal data latch, and if any port f pin is configured as an output, the value stored for that bit is driven onto the pin. a read of the port f data register returns the value at the pin only if the pin is configured as a discrete input. otherwise, the value read is the value stored in the register. the port f data register is a single register that can be accessed in two locations. when accessed at $yffa19, the register is referred to as portf0; when accessed at $yffa1b, the register is referred to as portf1. the register can be read or written at any time. it is unaffected by reset. the bits in this register control the direction of the pin drivers when the pins are configured as i/o. any bit in this register set to one configures the corresponding pin as an output. any bit in this register cleared to zero configures the corresponding pin as an input. this register can be read or written at any time. the bits in this register control the function of each port f pin. any bit cleared to zero defines the corre- sponding pin to be an i/o pin. any bit set to one defines the corresponding pin to be an interrupt request signal or modclk. the modclk signal has no function after reset. table 30 shows port f pin assignments. table 29 port e pin assignments pepar bit port e signal bus control signal pepa7 pe7 siz1 pepa6 pe6 siz0 pepa5 pe5 as pepa4 pe4 ds pepa3 pe3 rmc pepa2 pe2 a vec pepa1 pe1 dsa ck1 pepa0 pe0 dsa ck0 portf0, portf1 port f data register $yffa19, yffa1b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 reset: u u u u u u u u ddrf port f data direction register $yffa1d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 reset: 0 0 0 0 0 0 0 0 pfpar port f pin assignment register $yffa1f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used pfpa7 pfpa6 pfpa5 pfpa4 pfpa3 pfpa2 pfpa1 pfpa0 reset: data9 data9 data9 data9 data9 data9 data9 data9
mc68ck338 motorola MC68CK338TS/d 41 data bus pin 9 controls the state of this register following reset. if data9 is set to one during reset, the register is set to $ff, which defines all port f pins as interrupt request inputs. if data9 is cleared to zero during reset, this register is set to $00, defining all port f pins as i/o pins. 3.8 resets reset procedures handle system initialization and recovery from catastrophic failure. the mcu per- forms resets with a combination of hardware and software. the siml determines whether a reset is val- id, asserts control signals, performs basic system configuration based on hardware mode-select inputs, then passes control to the cpu. reset occurs when an active low logic level on the reset pin is clocked into the siml. resets are gat- ed by the clkout signal. asynchronous resets are assumed to be catastrophic. an asynchronous re- set can occur on any clock edge. synchronous resets are timed to occur at the end of bus cycles. if there is no clock when reset is asserted, reset does not occur until the clock starts. resets are clocked in order to allow completion of write cycles in progress at the time reset is asserted. reset is the highest-priority cpu32l exception. any processing in progress is aborted by the reset ex- ception, and cannot be restarted. only essential tasks are performed during reset exception processing. other initialization tasks must be accomplished by the exception handler routine. 3.8.1 siml reset mode selection the logic states of certain data bus pins during reset determine siml operating configuration. in addi- tion, the state of the modclk pin determines system clock source and the state of the bkpt pin de- termines what happens during subsequent breakpoint assertions. table 31 is a summary of reset mode selection options. table 30 port f pin assignments pfpar field port f signal alternate signal pfpa7 pf7 irq7 pfpa6 pf6 irq6 pfpa5 pf5 irq5 pfpa4 pf4 irq4 pfpa3 pf3 irq3 pfpa2 pf2 irq2 pfpa1 pf1 irq1 pfpa0 pf0 modclk
motorola mc68ck338 42 MC68CK338TS/d data lines have weak internal pull-up drivers. external bus loading can overcome the weak internal pull- up drivers on data bus lines, and hold pins low during reset. use an active device to hold data bus lines low. data bus configuration logic must release the bus before the first bus cycle after reset to prevent conflict with external memory devices. the first bus cycle occurs ten clkout cycles after reset is released. if external mode selection logic causes a conflict of this type, an isolation resistor on the driven lines may be required. 3.8.2 reset states of siml pins generally, while reset is asserted, siml pins either go to an inactive high-impedance state or are driven to their inactive states. after reset is released, mode selection occurs and reset exception pro- cessing begins. pins configured as inputs must be driven to the desired active state. pull-up or pull- down circuitry may be necessary. pins configured as outputs begin to function after reset is released. table 32 is a summary of siml pin states during reset. table 31 reset mode selection mode select pin default function (pin left high) alternate function (pin pulled low) data0 csboo t 16-bit csboo t 8-bit data1 cs0 cs1 cs2 br bg bga ck data2 cs3 cs4 cs5 fc0 fc1 fc2 data3 data4 data5 data6 data7 cs6 cs[7:6] cs[8:6] cs[9:6] cs[10:6] addr19 addr[20:19] addr[21:19] addr[22:19] addr[23:19] data8 dsa ck[1:0] a vec , ds , as siz[1:0] porte data9 irq[7:1] modclk portf data11 test mode disabled test mode enabled modclk vco = system clock extal = system clock bkpt background mode disabled background mode enabled
mc68ck338 motorola MC68CK338TS/d 43 3.8.3 functions of pins for other modules during reset generally, pins associated with modules other than the siml default to port functions, and input/output ports are set to input state. this is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. refer to individual module sec- tions in this manual for more information. 3.8.4 reset timing the reset input must be asserted for a specified minimum period in order for reset to occur. external reset assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. while reset is asserted, siml pins are either in a disabled high-impedance state or are driven to their inactive states. when an external device asserts reset for the proper period, reset control logic clocks the signal into an internal latch. the control logic drives the reset pin low for an additional 512 clkout cycles after it detects that the reset signal is no longer being externally driven, to guarantee this length of reset to the entire system. table 32 siml pin reset states pin(s) pin state while reset asserted pin state after reset released default function alternate function pin function pin state pin function pin state cs10 /addr23/eclk v dd cs10 v dd addr23 unknown cs[9:6] /addr[22:19]/pc[6:3] v dd cs[9:6] v dd addr[22:19] unknown addr[18:0] high-z addr[18:0] unknown addr[18:0] unknown as /pe5 high-z as output pe5 input avec /pe2 high-z avec input pe2 input berr high-z berr input berr input cs1 /bg v dd cs1 v dd bg v dd cs2 /bgack v dd cs2 v dd bgack input cs0 /br v dd cs0 v dd br input clkout output clkout output clkout output csboot v dd csboot v ss csboot v ss data[15:0] mode select data[15:0] input data[15:0] input ds /pe4 high-z ds output pe4 input dsack0 /pe0 high-z dsack0 input pe0 input dsack1 /pe1 high-z dsack1 input pe1 input cs[5:3] /fc[2:0]/pc[2:0] v dd cs[5:3] v dd fc[2:0] unknown halt high-z halt input halt input irq[7:1] /pf[7:1] high-z irq[7:1] input pf[7:1] input modclk/pf0 mode select modclk input pf0 input r/w high-z r/w output r/w output reset asserted reset input reset input rmc /pe3 high-z rmc output pe3 input siz[1:0]/pe[7:6] high-z siz[1:0] unknown pe[7:6] input tsc mode select tsc input tsc input
motorola mc68ck338 44 MC68CK338TS/d if an internal source asserts the reset signal, the reset control logic asserts reset for a minimum of 512 cycles. if the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert reset until the internal reset signal is negated. after 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy- cles. at the end of this 10-cycle period, the reset input is tested. when the input is at logic level one, reset exception processing begins. if, however, the reset input is at logic level zero, the reset control logic drives the pin low for another 512 cycles. at the end of this period, the pin again goes to high- impedance state for ten cycles, then it is tested again. the process repeats until reset is released. 3.8.5 power-on reset when the siml clock synthesizer is used to generate the system clock, power-on reset involves special circumstances related to application of system and clock synthesizer power. regardless of clock source, voltage must be applied to clock synthesizer power input pin v ddsyn in order for the mcu to operate. the following discussion assumes that v ddsyn is applied before and during reset. this mini- mizes crystal start-up time. when v ddsyn is applied at power-on, start-up time is affected by specific crystal parameters and by oscillator circuit design. v dd ramp-up time also affects pin state during reset. during power-on reset, an internal circuit in the siml drives the imb and external reset lines. the circuit releases the internal reset line as v dd ramps up to the minimum specified value, and siml pins are initialized. as v dd reaches a specified minimum value, the clock synthesizer vco begins operation and clock frequency ramps up to specified limp mode frequency. the external reset line remains asserted until the clock synthesizer pll locks and 512 clkout cycles elapse. the siml clock synthesizer provides clock signals to the other mcu modules. after the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. v dd ramp time and vco frequency ramp time determine how long these four cycles take. worst case is approximately 15 milliseconds. during this period, module port pins may be in an indeterminate state. while input-only pins can be put in a known state by means of external pull-up resistors, external logic on input/output or output-only pins must condition the lines during this time. active drivers require high-impedance buff- ers or isolation resistors to prevent conflict. 3.8.6 use of three-state control pin asserting the three-state control (tsc) input causes the mcu to put all output drivers in an inactive, high-impedance state. the signal must remain asserted for ten clock cycles in order for drivers to change state. there are certain constraints on use of tsc during power-on reset: ?when the internal clock synthesizer is used (modclk held high during reset), synthesizer ramp- up time affects how long the ten cycles take. worst case is approximately 20 ms from tsc asser- tion. ?when an external clock signal is applied (modclk held low during reset), pins go to high-imped- ance state as soon after tsc assertion as ten clock pulses have been applied to the extal pin. ?when tsc assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. once the output drivers change state, the mcu must be powered down and re- started before normal operation can resume. 3.9 interrupts interrupt recognition and servicing involve complex interaction between the cpu32l, the siml, and a device or module requesting interrupt service.
mc68ck338 motorola MC68CK338TS/d 45 the cpu32l provides seven levels of interrupt priority (1?), seven automatic interrupt vectors, and 200 assignable interrupt vectors. all interrupts with priorities less than seven can be masked by the in- terrupt priority (ip) field in status register. the cpu32l handles interrupts as a type of asynchronous expression. there are seven interrupt request signals (irq[7:1] ). these signals are used internally on the imb, and there are corresponding pins for external interrupt service requests. the cpu treats all interrupt re- quests as though they come from internal modules ?external interrupt requests are treated as interrupt service requests from the siml. each of the interrupt request signals corresponds to an interrupt priority level. irq1 has the lowest priority and irq7 the highest. interrupt recognition is determined by interrupt priority level and interrupt priority mask value. the inter- rupt priority mask consists of three bits in the cpu32l status register. binary values %000 to %111 pro- vide eight priority masks. masks prevent an interrupt request of a priority less than or equal to the mask value from being recognized and processed. irq7 , however, is always recognized, even if the mask value is %111. irq[7:1] are active-low level-sensitive inputs. the low on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected. irq7 is transition-sensitive as well as level-sensitive: a level 7 interrupt is not detected unless a falling edge transition is detected on the irq7 line. this prevents redundant servicing and stack overflow. a non-maskable interrupt is generated each time irq7 is asserted as well as each time the priority mask changes from %111 to a lower number while irq7 is asserted. interrupt requests are sampled on consecutive falling edges of the system clock. interrupt request input circuitry has hysteresis: to be valid, a request signal must be asserted for at least two consecutive clock periods. valid requests do not cause immediate exception processing, but are left pending. pending re- quests are processed at instruction boundaries or when exception processing of higher-priority excep- tions is complete. the cpu32l does not latch the priority of a pending interrupt request. if an interrupt source of higher priority makes a service request while a lower priority request is pending, the higher priority request is serviced. if an interrupt request with a priority equal to or lower than the current ip mask value is made, the cpu32l does not recognize the occurrence of the request. if simultaneous interrupt requests of dif- ferent priorities are made, and both have a priority greater than the mask value, the cpu32l recognizes the higher-level request. 3.9.1 interrupt acknowledge and arbitration when the cpu32l detects one or more interrupt requests of a priority higher than the interrupt priority mask value, it places the interrupt request level on the address bus and initiates a cpu space read cy- cle. the request level serves two purposes: it is decoded by modules or external devices that have re- quested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to them, and it is latched into the interrupt priority mask field in the cpu32l status register, to preclude further interrupts of lower priority during interrupt service. modules or external devices that have requested interrupt service must decode the interrupt priority mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority of the service request corresponds to the mask value. however, before modules or external devices respond, interrupt arbitration takes place.
motorola mc68ck338 46 MC68CK338TS/d arbitration is performed by means of serial contention between values stored in individual module inter- rupt arbitration (iarb) fields. each module that can make an interrupt service request, including the siml, has an iarb field in its configuration register. iarb fields can be assigned values from %0000 to %1111. in order to implement an arbitration scheme, each module that can initiate an interrupt ser- vice request must be assigned a unique, non-zero iarb field value during system initialization. arbitra- tion priorities range from %0001 (lowest) to %1111 (highest) ?if the cpu recognizes an interrupt service request from a source that has an iarb field value of %0000, a spurious interrupt exception is processed. warning do not assign the same arbitration priority to more than one module. when two or more iarb fields have the same non-zero value, the cpu32l interprets multiple vector numbers at the same time, with unpredictable consequences. because the ebi manages external interrupt requests, the siml iarb value is used for arbitration be- tween internal and external interrupt requests. the reset value of iarb for the siml is %1111, and the reset iarb value for all other modules is %0000. although arbitration is intended to deal with simultaneous requests of the same priority, it always takes place, even when a single source is requesting service. this is important for two reasons: the ebi does not transfer the interrupt acknowledge read cycle to the external bus unless the siml wins contention, and failure to contend causes the interrupt acknowledge bus cycle to be terminated early, by a bus error. when arbitration is complete, the module with the highest arbitration priority must terminate the bus cycle. internal modules place an interrupt vector number on the data bus and generate appropriate in- ternal cycle termination signals. in the case of an external interrupt request, after the interrupt acknowl- edge cycle is transferred to the external bus, the appropriate external device must decode the mask value and respond with a vector number, then generate data and size acknowledge (dsa ck ) termina- tion signals, or it must assert the autovector (a vec ) request signal. if the device does not respond in time, the ebi bus monitor asserts the bus error signal (berr ), and a spurious interrupt exception is taken. chip-select logic can also be used to generate internal a vec or dsa ck signals in response to interrupt requests from external devices. chip-select address match logic functions only after the ebi transfers an interrupt acknowledge cycle to the external bus following iarb contention. if a module makes an interrupt request of a certain priority, and the appropriate chip-select registers are programmed to gen- erate a vec or dsa ck signals in response to an interrupt acknowledge cycle for that priority level, chip- select logic does not respond to the interrupt acknowledge cycle, and the internal module supplies a vector number and generates internal cycle termination signals. for periodic timer interrupts, the pirql field in the periodic interrupt control register (picr) determines pit priority level. a pirql value of %000 means that pit interrupts are inactive. by hardware conven- tion, when the cpu32l receives simultaneous interrupt requests of the same level from more than one siml source (including external devices), the periodic interrupt timer is given the highest priority, fol- lowed by the irq pins. refer to 3.4.6 periodic interrupt timer for more information. 3.9.2 interrupt processing summary a summary of the interrupt processing sequence follows. when the sequence begins, a valid interrupt service request has been detected and is pending.
mc68ck338 motorola MC68CK338TS/d 47 a. the cpu finishes higher priority exception processing or reaches an instruction boundary. b. the processor state is stacked. the s bit in the status register is set, establishing supervisor access level, and bits t1 and t0 are cleared, disabling tracing. c. the interrupt acknowledge cycle begins: 1. fc[2:0] are driven to %111 (cpu space) encoding. 2. the address bus is driven as follows: addr[23:20] = %1111; addr[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge cpu space cycle; addr[15:4] = %111111111111; addr[3:1] = the priority of the interrupt request being acknowledged; and addr0 = %1. 3. the request level is latched from the address bus into the interrupt priority mask field in the status or condition code register. d. modules that have requested interrupt service decode the priority value on addr[3:1]. if request priority is the same as acknowledged priority, arbitration by iarb contention takes place. e. after arbitration, the interrupt acknowledge cycle is completed in one of the following ways: 1. when there is no contention (iarb = %0000), the spurious interrupt monitor asserts berr , and the cpu generates the spurious interrupt vector number. 2. the dominant interrupt source supplies a vector number and dsa ck signals appropriate to the access. the cpu acquires the vector number. 3. the a vec signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the cpu generates an autovector number corresponding to interrupt priority. 4. the bus monitor asserts berr and the cpu32l generates the spurious interrupt vector number. f. the vector number is converted to a vector address. g. the content of the vector address is loaded into the pc, and the processor transfers control to the exception handler routine. 3.10 factory test block the test submodule supports scan-based testing of the various mcu modules. it is integrated into the siml to support production testing. test submodule registers are intended for motorola use. register names and addresses are provided to indicate that these addresses are occupied. simltr system integration module test register $yffa02 simltre ? system integration module test register (e clock) $yffa08 tstmsra ? master shift register a $yffa30 tstmsrb ? master shift register b $yffa32 tstsc ? test module shift count $yffa34 tstrc ? test module repetition count $yffa36 creg ? test module control register $yffa38 dreg ? test module distributed register $yffa3a
motorola mc68ck338 48 MC68CK338TS/d 4 low-power central processor unit based on the powerful mc68020, the cpu32l processing module provides enhanced system perfor- mance and also uses the extensive software base for the motorola m68000 family. 4.1 overview the cpu32l is fully object-code compatible with the m68000 family, which excels at processing calcu- lation-intensive algorithms and supporting high-level languages. the cpu32l supports all of the mc68010 and most of the mc68020 enhancements, such as virtual memory support, loop mode oper- ation, instruction pipeline, and 32-bit mathematical operations. powerful addressing modes provide compatibility with existing software programs and increase the efficiency of high-level language compil- ers. special instructions, such as table lookup and interpolate and low-power stop, support the specific requirements of controller applications. also included is background debug mode, an alternate operat- ing mode that suspends normal operation and allows the cpu to accept debugging commands from the development system. ease of programming is an important consideration in using a microcontroller. the cpu32l instruction set is optimized for high performance. the eight 32-bit general-purpose data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long word) operations. ease of program checking and diagnosis is further enhanced by trace and trap capabilities at the instruction level. use of high-level languages is increasing as controller applications become more complex and control programs become larger. high-level languages aid rapid development of software, with less error, and are readily portable. the cpu32l instruction set supports high-level languages. 4.2 programming model the cpu32l has sixteen 32-bit general registers, a 32-bit program counter, one 32-bit supervisor stack pointer, a 16-bit status register, two alternate function code registers, and a 32-bit vector base register. the programming model of the cpu32l consists of a user model shown in figure 12 and a supervisor model shown in figure 13 , corresponding to the user and supervisor privilege levels. some instructions available at the supervisor level are not available at the user level, allowing the supervisor to protect system resources from uncontrolled access. bit s in the status register determines the privilege level. the user programming model remains unchanged from previous m68000 family microprocessors. ap- plication software written to run at the nonprivileged user level migrates without modification to the cpu32l from any m68000 platform. the move from sr instruction, however, is privileged in the cpu32l. it is not privileged in the m68000.
mc68ck338 motorola MC68CK338TS/d 49 figure 12 user programming model 16 31 15 0 87 d0 d2 d4 d6 d7 data registers address registers cpu32 user prog model 16 31 15 0 d1 d3 d5 a0 a1 a2 a3 a4 a5 a6 16 31 15 0 a7 (ssp) user stack pointer 31 0 pc program counter ccr condition code register 0 7
motorola mc68ck338 50 MC68CK338TS/d figure 13 supervisor programming model supplement 4.3 status register the status register contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. the lower byte containing the condition codes is the only portion of the register available at the user privilege level; it is referenced as the con- dition code register (ccr) in user programs. at the supervisor privilege level, software can access the full status register, including the interrupt priority mask and additional control bits. system byte t[1:0] ?trace enable s ?supervisor/user state bits [12:11] ?unimplemented ip[2:0] ?interrupt priority mask user byte (condition code register) bits [7:5] ?unimplemented x ?extend n ?negative z ?zero v ?overflow c ?carry sr status register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t1 t0 s 0 0 ip 0 0 0 x n z v c reset: 0 0 1 0 0 1 1 1 0 0 0 u u u u u 16 31 15 0 15 0 87 (ccr) 31 0 0 2 a7?(ssp) sr vbr sfc dfc supervisor stack pointer status register vector base register alternate function code registers cpu32 supv prog model
mc68ck338 motorola MC68CK338TS/d 51 4.4 data types six basic data types are supported: ?bits ?packed binary coded decimal digits ?byte integers (8 bits) ?word integers (16 bits) ?long word integers (32 bits) ?quad word integers (64 bits) 4.5 addressing modes addressing in the cpu32l is register-oriented. most instructions allow the results of the specified op- eration to be placed either in a register or directly in memory. this flexibility eliminates the need for extra instructions to store register contents in memory. the cpu32l supports seven basic addressing modes: ?register direct ?register indirect ?register indirect with index ?program counter indirect with displacement ?program counter indirect with index ?absolute ?immediate included in the register indirect addressing modes are the capabilities to post-increment, predecrement, and offset. the program counter relative mode also has index and offset capabilities. in addition to these addressing modes, many instructions implicitly specify the use of the status register, stack point- er, or program counter. 4.6 instruction set summary table 33 provides a summary of the cpu32l instruction set.
motorola mc68ck338 52 MC68CK338TS/d table 33 instruction set summary instruction syntax operand size operation abcd dn, dn - (an), - (an) 8 8 source 10 + destination 10 + x t destination add dn, , dn 8, 16, 32 8, 16, 32 source + destination t destination adda , an 16, 32 source + destination t destination addi #, 8, 16, 32 immediate data + destination t destination addq # , 8, 16, 32 immediate data + destination t destination addx dn, dn - (an), - (an) 8, 16, 32 8, 16, 32 source + destination + x t destination and , dn dn, 8, 16, 32 8, 16, 32 source destination t destination andi # , 8, 16, 32 data destination t destination andi to ccr # , ccr 8 source ccr t ccr andi to sr1 1 # , sr 16 source sr t sr asl dn, dn # , dn 8, 16, 32 8, 16, 32 16 asr dn, dn # , dn 8, 16, 32 8, 16, 32 16 bcc label 8, 16, 32 if condition true, then pc + d t pc bchg dn, # , 8, 32 8, 32 bclr dn, # , 8, 32 8, 32 0 t bit of destination bgnd none none if background mode enabled, then enter background mode, else format/vector t - (ssp); pc t - (ssp); sr t - (ssp); (vector) t pc bkpt # none if breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction bra label 8, 16, 32 pc + d t pc bset dn, # , 8, 32 8, 32 1 t bit of destination bsr label 8, 16, 32 sp - 4 t sp; pc t (sp); pc + d t pc btst dn, # , 8, 32 8, 32 chk , dn 16, 32 if dn < 0 or dn > (ea), then chk exception chk2 , rn 8, 16, 32 if rn < lower bound or rn > upper bound, then chk exception clr 8, 16, 32 0 t destination cmp , dn 8, 16, 32 (destination - source), ccr shows results cmpa , an 16, 32 (destination - source), ccr shows results cmpi # , 8, 16, 32 (destination - data), ccr shows results x/c 0 x/c bit number ? of destination () z bit of destination tt bit number ? of destination () z; t bit number ? of destination () z; t bit number ? of destination () z t
mc68ck338 motorola MC68CK338TS/d 53 cmpm (an) + , (an) + 8, 16, 32 (destination - source), ccr shows results cmp2 , rn 8, 16, 32 lower bound rn upper bound, ccr shows result dbcc dn, label 16 if condition false, then dn - 1 t pc; if dn 1 ( - 1), then pc + d t pc divs/divu , dn 32/16 t 16 : 16 destination / source t destination (signed or unsigned) divsl/divul , dr : dq , dq , dr : dq 64/32 t 32 : 32 32/32 t 32 32/32 t 32 : 32 destination / source t destination (signed or unsigned) eor dn, 8, 16, 32 source ? destination t destination eori # , 8, 16, 32 data ? destination t destination eori to ccr # , ccr 8 source ? ccr t ccr eori to sr 1 # , sr 16 source ? sr t sr exg rn, rn 32 rn t rn ext dn dn 8 t 16 16 t 32 sign extended destination t destination extb dn 8 t 32 sign extended destination t destination illegal none none ssp - 2 t ssp; vector offset t (ssp); ssp - 4 t ssp; pc t (ssp); ssp - 2 t ssp; sr t (ssp); illegal instruction vector address t pc jmp none destination t pc jsr none sp - 4 t sp; pc t (sp); destination t pc lea , an 32 t an link an, # d 16, 32 sp - 4 t sp, an t (sp); sp t an, sp + d t sp lpstop 1, 2 # 16 data t sr; interrupt mask t ebi; stop lsl dn, dn # , dn 8, 16, 32 8, 16, 32 16 lsr dn, dn #, dn 8, 16, 32 8, 16, 32 16 move , 8, 16, 32 source t destination movea , an 16, 32 t 32 source t destination movea 1 usp, an an, usp 32 32 usp t an an t usp move from ccr ccr, 16 ccr t destination move to ccr , ccr 16 source t ccr move from sr 1 sr, 16 sr t destination move to sr 1 , sr 16 source t sr move usp 1 usp, an an, usp 32 32 usp t an an t usp movec 1 rc, rn rn, rc 32 32 rc t rn rn t rc table 33 instruction set summary (continued) instruction syntax operand size operation x/c 0 x/c 0
motorola mc68ck338 54 MC68CK338TS/d movem list, , list 16, 32 16, 32 t 32 listed registers t destination source t listed registers movep dn, (d16, an) (d16, an), dn 16, 32 dn [31 : 24] t (an + d); dn [23 : 16] t (an + d + 2); dn [15 : 8] t (an + d + 4); dn [7 : 0] t (an + d + 6) (an + d) t dn [31 : 24]; (an + d + 2) t dn [23 : 16]; (an + d + 4) t dn [15 : 8]; (an + d + 6) t dn [7 : 0] moveq #, dn 8 t 32 immediate data t destination moves 1 rn, , rn 8, 16, 32 rn t destination using dfc source using sfc t rn muls/mulu , dn , dl , dh : dl 16 * 16 t 32 32 * 32 t 32 32 * 32 t 64 source * destination t destination (signed or unsigned) nbcd 8 8 0 - destination 10 - x t destination neg 8, 16, 32 0 - destination t destination negx 8, 16, 32 0 - destination - x t destination nop none none pc + 2 t pc not 8, 16, 32 destination t destination or , dn dn, 8, 16, 32 8, 16, 32 source + destination t destination ori #, 8, 16, 32 data + destination t destination ori to ccr #, ccr 16 source + ccr t sr ori to sr 1 #, sr 16 source ; sr t sr pea 32 sp - 4 t sp; t sp reset 1 none none assert reset line rol dn, dn #, dn 8, 16, 32 8, 16, 32 16 ror dn, dn #, dn 8, 16, 32 8, 16, 32 16 roxl dn, dn #, dn 8, 16, 32 8, 16, 32 16 roxr dn, dn #, dn 8, 16, 32 8, 16, 32 16 rtd #d 16 (sp) t pc; sp + 4 + d t sp rte 1 none none (sp) t sr; sp + 2 t sp; (sp) t pc; sp + 4 t sp; restore stack according to format rtr none none (sp) t ccr; sp + 2 t sp; (sp) t pc; sp + 4 t sp rts none none (sp) t pc; sp + 4 t sp sbcd dn, dn - (an), - (an) 8 8 destination10 - source10 - x t destination table 33 instruction set summary (continued) instruction syntax operand size operation c c c x c x
mc68ck338 motorola MC68CK338TS/d 55 1. privileged instruction. 2. two lpstop modes are supported. the first lpstop mode is the normal lpstop in which the system clock on the chip is stopped, shutting down all imb modules with the exception of some parts of the siml and clkout. the second lpstop mode causes the system clock to be stopped only at the cpu32l, when the lpstop instruction is executed by the cpu32l. as with the normal lpstop operation, the cpu32l can be restarted by an interrupt, a trace, or a reset exception. scc 8 if condition true, then destination bits are set to 1; else, destination bits are cleared to 0 stop 1 # 16 data t sr; stop sub , dn dn, 8, 16, 32 destination - source t destination suba , an 16, 32 destination - source t destination subi #, 8, 16, 32 destination - data t destination subq #, 8, 16, 32 destination - data t destination subx dn, dn - (an), - (an) 8, 16, 32 8, 16, 32 destination - source - x t destination swap dn 16 tas 8 destination tested condition codes bit 7 of destination tbls/tblu , dn dym : dyn, dn 8, 16, 32 dyn - dym t temp (temp * dn [7 : 0]) t temp (dym * 256) + temp t dn tblsn/tblun , dn dym : dyn, dn 8, 16, 32 dyn - dym t temp (temp * dn [7 : 0]) / 256 t temp dym + temp t dn trap # none ssp - 2 t ssp; format/vector offset t (ssp); ssp - 4 t ssp; pc t (ssp); sr t (ssp); vector address t pc trapcc none # none 16, 32 if cc true, then trap exception trapv none none if v set, then overflow trap exception tst 8, 16, 32 source - 0, to set condition codes unlk an 32 an t sp; (sp) t an, sp + 4 t sp table 33 instruction set summary (continued) instruction syntax operand size operation msw lsw
motorola mc68ck338 56 MC68CK338TS/d 4.7 background debugging mode the background debugger on the cpu32l is implemented in cpu microcode. the background debug- ging commands are summarized in table 34 . table 34 background debugging mode commands command mnemonic description read d/a register rdreg/rareg read the selected address or data register and return the results through the serial interface. write d/a register wdreg/wareg the data operand is written to the specified address or data register. read system register rsreg the specified system control register is read. all regis- ters that can be read in supervisor mode can be read in background mode. write system register wsreg the operand data is written into the specified system control register. read memory location read read the sized data at the memory location specified by the long-word address. the source function code register (sfc) determines the address space access- ed. write memory location write write the operand data to the memory location speci- fied by the long-word address. the destination function code (dfc) register determines the address space ac- cessed. dump memory block dump used in conjunction with the read command to dump large blocks of memory. an initial read is executed to set up the starting address of the block and retrieve the first result. subsequent operands are retrieved with the dump command. fill memory block fill used in conjunction with the write command to fill large blocks of memory. initially, a write is executed to set up the starting address of the block and supply the first operand. the fill command writes subse- quent operands. resume execution go the pipe is flushed and refilled before resuming in- struction execution at the current pc. patch user code call current program counter is stacked at the location of the current stack pointer. instruction execution begins at user patch code. reset peripherals rst asserts reset for 512 clock cycles. the cpu is not reset by this command. synonymous with the cpu re- set instruction. no operation nop nop performs no operation and can be used as a null command.
mc68ck338 motorola MC68CK338TS/d 57 5 queued serial module the qsm contains two serial interfaces, the queued serial peripheral interface (qspi) and the serial communication interface (sci). figure 14 shows the qsm block diagram. figure 14 qsm block diagram 5.1 overview the qspi provides easy peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. four programmable peripheral chip- select pins provide addressability for up to 16 peripheral devices. a self-contained ram queue allows up to 16 serial transfers of 8 to 16 bits each, or transmission of a 256-bit data stream without cpu in- tervention. a special wraparound mode supports continuous sampling of a serial peripheral, with auto- matic qspi ram updating, which makes the interface to a/d converters more efficient. the sci provides a standard non-return to zero (nrz) mark/space format. it operates in either full- or half-duplex mode. there are separate transmitter and receiver enable bits and dual data buffers. a modulus-type baud rate generator provides rates from 55 to 451 kbaud with a 14.44-mhz system clock. word length of either eight or nine bits is software selectable. optional parity generation and detection provide either even or odd parity check capability. advanced error detection circuitry catches glitches of up to 1/16 of a bit time in duration. wakeup functions allow the cpu to run uninterrupted until mean- ingful data is available. table 35 shows the address map of the qsm. qspi interface logic sci miso/pqs0 mosi/pqs1 sck/pqs2 pcs0/ss /pqs3 pcs1/pqs4 pcs2/pqs5 pcs3/pqs6 txd/pqs7 rxd port qs qsm block imb
motorola mc68ck338 58 MC68CK338TS/d 5.2 address map the ?ccess?column in the qsm address map in table 35 indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the supv bit in the qsmcr. notes: 1. y = m111, where m is the logic state of the mm bit in the simlcr. table 35 qsm address map access address 15 8 7 0 s $yffc00 1 qsm module configuration register (qsmcr) s $yffc02 qsm test register (qtest) s $yffc04 qsm interrupt level register (qilr) qsm interrupt vector register (qivr) s/u $yffc06 not used s/u $yffc08 sci control 0 register (sccr0) s/u $yffc0a sci control 1 register (sccr1) s/u $yffc0c sci status register (scsr) s/u $yffc0e sci data register (scdr) s/u $yffc10 not used s/u $yffc12 not used s/u $yffc14 not used pqs data register (portqs) s/u $yffc16 pqs pin assignment register (pqspar) pqs data direction register (ddrqs) s/u $yffc18 spi control register 0 (spcr0) s/u $yffc1a spi control register 1 (spcr1) s/u $yffc1c spi control register 2 (spcr2) s/u $yffc1e spi control register 3 (spcr3) spi status register (spsr) s/u $yffc20 $yffcff not used s/u $yffd00 $yffd1f receive ram (rr[0:f]) s/u $yffd20 $yffd3f transmit ram (tr[0:f]) s/u $yffd40 $yffd4f command ram (cr[0:f])
mc68ck338 motorola MC68CK338TS/d 59 5.3 pin function table 36 is a summary of the functions of the qsm pins when they are not configured for general-pur- pose i/o. the qsm data direction register (ddrqs) designates each pin except rxd as an input or output. 5.4 qsm registers qsm registers are divided into four categories: qsm global registers, qsm pin control registers, qspi submodule registers, and sci submodule registers. the qspi and sci registers are defined in separate sections below. writes to unimplemented register bits have no meaning or effect, and reads from unim- plemented bits always return a logic zero value. the module mapping bit of the siml configuration register (simlcr) defines the most significant bit (addr23) of the address, shown in each register figure as y (y = $7 or $f). this bit, concatenated with the rest of the address given, forms the absolute address of each register. refer to the siml section of this technical summary for more information about how the state of mm affects the system. 5.4.1 global registers the qsm global registers contain system parameters used by both the qspi and the sci submodules. these registers contain the bits and fields used to configure the qsm. the qsmcr contains parameters for the qsm/cpu/intermodule bus (imb) interface. table 36 qsm pin functions pin mode pin function miso master serial data input to qspi qspi pins slave serial data output from qspi mosi master serial data output from qspi slave serial data input to qspi sck master clock output from qspi slave clock input to qspi pcs0/ss master input: assertion causes mode fault output: selects peripherals slave input: selects the qspi pcs[3:1] master output: selects peripherals slave none sci pins txd transmit serial data output from sci rxd receive serial data input to sci qsmcr qsm configuration register $yffc00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop frz1 frz0 0 0 0 0 0 supv 0 0 0 iarb reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola mc68ck338 60 MC68CK338TS/d stop ?stop enable 0 = normal qsm clock operation 1 = qsm clock operation stopped stop places the qsm in a low-power state by disabling the system clock in most parts of the module. the qsmcr is the only register guaranteed to be readable while stop is asserted. the qspi ram is not readable. however, writes to ram or any register are guaranteed to be valid while stop is assert- ed. stop can be negated by the cpu and by reset. the system software must stop each submodule before asserting stop to avoid complications at re- start and to avoid data corruption. the sci submodule receiver and transmitter should be disabled, and the operation should be verified for completion before asserting stop. the qspi submodule should be stopped by asserting the halt bit in spcr3 and by asserting stop after the halta flag is set. frz1 ?freeze 1 0 = ignore the freeze signal on the imb 1 = halt the qspi (on a transfer boundary) frz1 determines what action is taken by the qspi when the freeze signal of the imb is asserted. freeze is asserted whenever the cpu enters the background mode. frz0 ?freeze 0 reserved bits [12:8] ?not implemented supv ?supervisor/unrestricted 0 = user access 1 = supervisor access supv defines the assignable qsm registers as either supervisor-only data space or unrestricted data space. iarb ?interrupt arbitration identification number the iarb field is used to arbitrate between simultaneous interrupt requests of the same priority. each module that can generate interrupt requests must be assigned a unique, non-zero iarb field value. refer to 3.9 interrupts for more information. qtest ? qsm test register $yffc02 qtest is used during factory testing of the qsm. accesses to qtest must be made while the mcu is in test mode. qilr determines the priority level of interrupts requested by the qsm and the vector used when an in- terrupt is acknowledged. ilqspi ?interrupt level for qspi ilqspi determines the priority of qspi interrupts. this field must be given a value between $0 (inter- rupts disabled) to $7 (highest priority). qilr ? qsm interrupt levels register $yffc04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 ilqspi ilsci qivr reset: 0 0 0 0 0 0 0 0
mc68ck338 motorola MC68CK338TS/d 61 ilsci ?interrupt level of sci ilsci determines the priority of sci interrupts. this field must be given a value between $0 (interrupts disabled) to $7 (highest priority). if ilqspi and ilsci are the same nonzero value, and both submodules simultaneously request inter- rupt service, qspi has priority. at reset, qivr is initialized to $0f, which corresponds to the uninitialized interrupt vector in the excep- tion table. this vector is selected until qivr is written. a user-defined vector ($40?ff) should be writ- ten to qivr during qsm initialization. after initialization, qivr determines which two vectors in the exception vector table are to be used for qsm interrupts. the qspi and sci submodules have separate interrupt vectors adjacent to each other. both submodules use the same interrupt vector with the least significant bit (lsb) determined by the submodule causing the interrupt. the value of intv0 used during an interrupt-acknowledge cycle is supplied by the qsm. during an in- terrupt-acknowledge cycle, intv[7:1] are driven on data[7:1] imb lines. data0 is negated for an sci interrupt and asserted for a qspi interrupt. writes to intv0 have no meaning or effect. reads of intv0 return a value of one. 5.4.2 pin control registers the qsm uses nine pins, eight of which form a parallel port (portqs) on the mcu. although these pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose i/o on a pin-by-pin basis. pins used for general-purpose i/o must not be assigned to the qspi by register pqspar. to avoid driving incorrect data, the first byte to be output must be written before ddrqs is configured. ddrqs must then be written to determine the direction of data flow and to output the value contained in register portqs. subsequent data for output is written to portqs. portqs latches i/o data. writes drive pins defined as outputs. reads return data present on the pins. to avoid driving undefined data, first write a byte to portqs, then configure ddrqs. qivr qsm interrupt vector register $yffc05 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 qilr intv reset: 0 0 0 0 1 1 1 1 portqs port qs data register $yffc14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pqs7 pqs6 pqs5 pqs4 pqs3 pqs2 pqs1 pqs0 reset: 0 0 0 0 0 0 0 0
motorola mc68ck338 62 MC68CK338TS/d clearing a bit in the pqspar assigns the corresponding pin to general-purpose i/o; setting a bit as- signs the pin to the qspi. the pqspar does not affect operation of the sci. table 37 displays pqs- par pin assignments. ddrqs determines whether pins are inputs or outputs. clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. ddrqs affects both qspi function and i/o function. table 38 shows the effect of ddrqs on qsm pin functions. notes: 1. pqs2 is a digital i/o pin unless the spi is en- abled (spe in spcr1 set), in which case it be- comes spi serial clock sck. 2. pqs7 is a digital i/o pin unless the sci trans- mitter is enabled (te in sccr1 = 1), in which case it becomes sci serial output txd. pqspar port qs pin assignment register $yffc16 ddrqs ? port qs data direction register $yffc17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 pqspa6 pqspa5 pqspa4 pqspa3 0 pqspa1 pqspa0 ddqs7 ddqs6 ddqs5 ddqs4 ddqs3 ddqs2 ddqs1 ddqs0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 37 pqspar pin assignments pqspar field pqspar bit pin function pqspa0 0 pqs0 1 miso pqspa1 0 pqs1 1 mosi pqspa2 0 pqs2 1 1 sck pqspa3 0 pqs3 1 pcs0/ss pqspa4 0 pqs4 1 pcs1 pqspa5 0 pqs5 1 pcs2 pqspa6 0 pqs6 1 pcs3 pqspa7 0 pqs7 2 1 txd
mc68ck338 motorola MC68CK338TS/d 63 ddrqs determines the direction of the txd pin only when the sci transmitter is disabled. when the sci transmitter is enabled, the txd pin is an output. notes: 1. pqs2 is a digital i/o pin unless the spi is enabled (spe in spcr1 set), in which case it becomes spi serial clock sck. 2. pqs7 is a digital i/o pin unless the sci transmitter is enabled (te in sccr1 = 1), in which case it becomes sci serial output txd. table 38 effect of ddrqs on qsm pin function qsm pin mode ddrqs bit bit state pin function miso master ddq0 0 serial data input to qspi 1 disables data input slave 0 disables data output 1 serial data output from qspi mosi master ddq1 0 disables data output 1 serial data output from qspi slave 0 serial data input to qspi 1 disables data input sck 1 master ddq2 0 disables clock output 1 clock output from qspi slave 0 clock input to qspi 1 disables clock input pcs0/ss master ddq3 0 assertion causes mode fault 1 chip-select output slave 0 qspi slave select input 1 disables select input pcs[3:1] master ddq[4:6] 0 disables chip-select output 1 chip-select output slave 0 inactive 1 inactive txd 2 transmit ddq7 x serial data output from sci rxd receive none na serial data input to sci
motorola mc68ck338 64 MC68CK338TS/d 5.5 qspi submodule the qspi submodule communicates with external devices through a synchronous serial bus. the qspi is fully compatible with the serial peripheral interface (spi) systems found on other motorola products. figure 15 shows a block diagram of the qspi. figure 15 qspi block diagram qspi block control registers end queue pointer queue pointer status register delay counter comparator programmable logic array 80-byte qspi ram chip select command done 4 4 2 baud rate generator pcs[2:1] pcs0/ss miso mosi sck m s m s 8/16-bit shift register rx/tx data register msb lsb 4 4 queue control block control logic a d d r e s s r e g i s t e r
mc68ck338 motorola MC68CK338TS/d 65 5.5.1 qspi pins seven pins are associated with the qspi. when not needed for a qspi function, they can be configured as general-purpose i/o pins. the pcs0/ss pin can function as a peripheral chip select output, slave select input, or general-purpose i/o. refer to table 39 for qspi input and output pins and their func- tions. 5.5.2 qspi registers the programmer's model for the qspi submodule consists of the qsm global and pin control registers, four qspi control registers, one status register, and the 80-byte qspi ram. the cpu can read and write to registers and ram. the four control registers must be initialized before the qspi is enabled to ensure defined operation. spcr1 should be written last because it contains qspi enable bit spe. asserting this bit starts the qspi. the qspi control registers are reset to a de- fined state and can then be changed by the cpu. reset values are shown below each register. table 40 shows a memory map of the qspi. writing a different value into any control register except spcr2 while the qspi is enabled disrupts op- eration. spcr2 is buffered to prevent disruption of the current serial transfer. after completion of the current serial transfer, the new spcr2 values become effective. writing the same value into any control register except spcr2 while the qspi is enabled has no effect on qspi operation. rewriting newqp[3:0] in spcr2 causes execution to restart at the designated location. table 39 qspi pins pin name(s) mnemonic(s) mode function master in slave out miso master slave serial data input to qspi serial data output from qspi master out slave in mosi master slave serial data output from qspi serial data input to qspi serial clock sck master slave clock output from qspi clock input to qspi peripheral chip selects pcs[3:1] master select peripherals peripheral chip select slave select pcs0 ss master master slave selects peripheral causes mode fault initiates serial transfer table 40 qspi memory map address name usage $yffc18 spcr0 qspi control register 0 $yffc1a spcr1 qspi control register 1 $yffc1c spcr2 qspi control register 2 $yffc1e spcr3 qspi control register 3 $yffc1f spsr qspi status register $yffd00 rr[0:f] qspi receive data (16 words) $yffd20 tr[0:f] qspi transmit data (16 words) $yffd40 cr[0:f] qspi command control (8 words)
motorola mc68ck338 66 MC68CK338TS/d spcr0 contains parameters for configuring the qspi before it is enabled. the cpu can read and write this register. the qsm has read-only access. mstr ?master/slave mode select 0 = qspi is a slave device and only responds to externally generated serial data. 1 = qspi is system master and can initiate transmission to external spi devices. mstr configures the qspi for either master or slave mode operation. this bit is cleared on reset and may only be written by the cpu. womq ?wired-or mode for qspi pins 0 = outputs have normal mos drivers. 1 = pins designated for output by ddrqs have open-drain drivers. womq allows the wired-or function to be used on qspi pins, regardless of whether they are used as general-purpose outputs or as qspi outputs. womq affects the qspi pins regardless of whether the qspi is enabled or disabled. bits[3:0] ?bits per transfer in master mode, when bitse in a command is set, the bits[3:0] field determines the number of data bits transferred. when bitse is cleared, eight bits are transferred. reserved values default to eight bits. in slave mode, the command ram is not used and the setting of bitse has no effect on qspi transfers. instead, the bits[3:0] field determines the number of bits the qspi will receive during each transfer be- fore storing the received data. table 41 shows the number of bits per transfer. spcr0 qspi control register 0 $yffc18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mstr womq bits[3:0] cpol cpha spbr[7:0] reset: 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 table 41 bits per transfer bits[3:0] bits per transfer 0000 16 0001 reserved 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15
mc68ck338 motorola MC68CK338TS/d 67 cpol ?clock polarity 0 = the inactive state value of sck is logic level zero. 1 = the inactive state value of sck is logic level one. cpol is used to determine the inactive state value of the serial clock (sck). it is used with cpha to produce a desired clock/data relationship between master and slave devices. cpha ?clock phase 0 = data is captured on the leading edge of sck and changed on the following edge of sck. 1 = data is changed on the leading edge of sck and captured on the following edge of sck. cpha determines which edge of sck causes data to change and which edge causes data to be cap- tured. cpha is used with cpol to produce a desired clock/data relationship between master and slave devices. cpha is set at reset. spbr[7:0] ?serial clock baud rate the qspi uses a modulus counter to derive sck baud rate from the mcu system clock. baud rate is selected by writing a value from 2 to 255 into the spbr[7:0] field. the following equation determines the sck baud rate: or giving spbr[7:0] a value of zero or one disables the baud rate generator. sck is disabled and as- sumes its inactive state value. no serial transfers occur. at reset, baud rate is initialized to one eighth of the system clock frequency. spcr1 contains parameters for configuring the qspi before it is enabled. the cpu can read and write this register, but the qsm has read access only, except for spe, which is automatically cleared by the qspi after completing all serial transfers, or when a mode fault occurs. spe ?qspi enable 0 = qspi is disabled. qspi pins can be used for general-purpose i/o. 1 = qspi is enabled. pins allocated by pqspar are controlled by the qspi. dsckl[6:0] ?delay before sck when the dsck bit in command ram is set, this field determines the length of delay from pcs valid to sck transition. pcs can be any of the four peripheral chip-select pins. the following equation deter- mines the actual delay before sck: where dsckl[6:0] equals {1, 2, 3,..., 127}. when the dsck value of a queue entry equals zero, then dsckl[6:0] is not used. instead, the pcs valid-to-sck transition is one-half sck period. sprc1 qspi control register 1 $yffc1a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spe dsckl[6:0] dtl[7:0] reset: 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 sck baud rate system clock 2 spbr[7:0] ------------------------------------- = spbr[7:0] system clock 2 sck baud rate desired -------------------------------------------------------------------------- = pcs to sck delay dsckl[6:0] system clock ------------------------------------ =
motorola mc68ck338 68 MC68CK338TS/d dtl[7:0] ?length of delay after transfer when the dt bit in command ram is set, this field determines the length of delay after serial transfer. the following equation is used to calculate the delay: where dtl equals {1, 2, 3,..., 255}. a zero value for dtl[7:0] causes a delay-after-transfer value of 8192/system clock. if dt equals zero, a standard delay is inserted. delay after transfer can be used to provide a peripheral deselect interval. a delay can also be inserted between consecutive transfers to allow serial a/d converters to complete conversion. spcr2 contains qspi configuration parameters. the cpu can read and write this register; the qsm has read access only. writes to spcr2 are buffered. a write to spcr2 that changes a bit value while the qspi is operating is ineffective on the current serial transfer, but becomes effective on the next se- rial transfer. reads of spcr2 return the current value of the register, not of the buffer. spifie ?spi finished interrupt enable 0 = qspi interrupts disabled 1 = qspi interrupts enabled spifie enables the qspi to generate a cpu interrupt upon assertion of the status flag spif. wren ?wrap enable 0 = wraparound mode disabled 1 = wraparound mode enabled wren enables or disables wraparound mode. wrto ?wrap to when wraparound mode is enabled, after the end of queue has been reached, wrto determines which address the qspi executes. bit 12 ?not implemented endqp[3:0] ?ending queue pointer this field contains the last qspi queue address. bits [7:4] ?not implemented newqp[3:0] ?new queue pointer value this field contains the first qspi queue address. spcr2 qspi control register 2 $yffc1c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spifie wren wrto 0 endqp[3:0] 0 0 0 0 newqp[3:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay after transfer 32 dtl[7:0] system clock ------------------------------------ = standard delay after transfer 17 system clock ------------------------------------ =
mc68ck338 motorola MC68CK338TS/d 69 spcr3 contains qspi configuration parameters. the cpu can read and write spcr3, but the qsm has read-only access. bits [15:11] ?not implemented loopq ?qspi loop mode 0 = feedback path disabled 1 = feedback path enabled loopq controls feedback on the data serializer for testing. hmie ?halta and modf interrupt enable 0 = halta and modf interrupts disabled 1 = halta and modf interrupts enabled hmie controls cpu interrupts caused by the halta status flag or the modf status flag in spsr. halt ?halt 0 = halt not enabled 1 = halt enabled when halt is asserted, the qspi stops on a queue boundary. it is in a defined state from which it can later be restarted. spsr contains qspi status information. only the qspi can assert the bits in this register. the cpu reads this register to obtain status information and writes it to clear status flags. spif ?qspi finished flag 0 = qspi not finished 1 = qspi finished spif is set after execution of the command at the address in endqp[3:0]. modf ?mode fault flag 0 = normal operation 1 = another spi node requested to become the network spi master while the qspi was enabled in master mode (ss input taken low). the qspi asserts modf when the qspi is the serial master (mstr = 1) and the ss input pin is negat- ed by an external driver. halta ?halt acknowledge flag 0 = qspi not halted 1 = qspi halted halta is asserted when the qspi halts in response to cpu assertion of halt. bit 4 ?not implemented spcr3 qspi control register $yffc1e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 loopq hmie halt spsr reset: 0 0 0 0 0 0 0 0 spsr qspi status register $yffc1f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spcr3 spif modf halta 0 cptqp[3:0] reset: 0 0 0 0 0 0 0 0
motorola mc68ck338 70 MC68CK338TS/d cptqp[3:0] ?completed queue pointer cptqp[3:0] points to the last command executed. it is updated when the current command is complete. when the first command in a queue is executing, cptqp[3:0] contains either the reset value ($0) or a pointer to the last command completed in the previous queue. 5.5.3 qspi ram the qspi contains an 80-byte block of dual-access static ram that is used by both the qspi and the cpu. the ram is divided into three segments: receive data, transmit data, and command control data. receive data is information received from a serial device external to the mcu. transmit data is infor- mation stored by the cpu for transmission to an external peripheral. command control data is used to perform the transfer. figure 16 displays the organization of the ram. figure 16 qspi ram once the cpu has set up the queue of qspi commands and enabled the qspi, the qspi can operate independently of the cpu. the qspi executes all of the commands in its queue, sets a flag indicating that it is finished, and then either interrupts the cpu or waits for cpu intervention. it is possible to ex- ecute a queue of commands repeatedly without cpu intervention. rr[0:f] ? receive data ram $yffd00 data received by the qspi is stored in this segment. the cpu reads this segment to retrieve data from the qspi. data stored in receive ram is right-justified. unused bits in a receive queue entry are set to zero by the qspi upon completion of the individual queue entry. the cpu can access the data using byte, word, or long-word addressing. the cptqp[3:0] value in spsr shows which queue entries have been executed. the cpu uses this information to determine which locations in receive ram contain valid data before reading them. tr[0:f] ? transmit data ram $yffd20 data that is to be transmitted by the qspi is stored in this segment. the cpu usually writes one word of data into this segment for each queue command to be executed. qspi ram map receive ram transmit ram 500 51e 520 53e word 540 54f command ram byte word rr0 rr1 rr2 rrd rre rrf tr0 tr1 tr2 trd tre trf cr0 cr1 cr2 crd cre crf
mc68ck338 motorola MC68CK338TS/d 71 information to be transmitted must be written to transmit data ram in a right-justified format. the qspi cannot modify information in the transmit data ram. the qspi copies the information to its data serial- izer for transmission. information remains in transmit ram until overwritten. command ram is used by the qspi when in master mode. the cpu writes one byte of control infor- mation to this segment for each qspi command to be executed. the qspi cannot modify information in command ram. command ram consists of 16 bytes. each byte is divided into two fields. the peripheral chip-select field enables peripherals for transfer. the command control field provides transfer options. a maximum of 16 commands can be in the queue. queue execution by the qspi proceeds from the address in newqp[3:0] through the address in endqp[3:0]. (both of these fields are in spcr2). cont ?continue 0 = control of chip selects returned to portqs after transfer is complete. 1 = peripheral chip selects remain asserted after transfer is complete. bitse ?bits per transfer enable 0 = 8 bits 1 = number of bits set in bits[3:0] field of spcr0 dt ?delay after transfer the qspi provides a variable delay at the end of serial transfer to facilitate the interface with peripherals that have a latency requirement. the delay between transfers is determined by the spcr1 dtl[6:0] field. dsck ?pcs to sck delay 0 = pcs valid to sck transition is one-half sck. 1 = spcr1 dsckl[6:0] field specifies delay from pcs valid to sck. pcs[3:0] ?peripheral chip select use peripheral chip-select bits to select an external device for serial data transfer. more than one pe- ripheral chip select can be activated at a time, and more than one peripheral chip can be connected to each pcs pin, provided that proper fanout is observed. notes: 1. the pcs0 bit represents the dual-function pcs0/ss . cr[0:f] ? command ram $yffd40 76543210 cont bitse dt dsck pcs3 pcs2 pcs1 pcs0 1 cont bitse dt dsck pcs3 pcs2 pcs1 pcs0 1 command control peripheral chip select
motorola mc68ck338 72 MC68CK338TS/d 5.5.4 operating modes the qspi operates in either master or slave mode. master mode is used when the mcu originates data transfers. slave mode is used when an external device initiates serial transfers to the mcu through the qspi. switching between the modes is controlled by mstr in spcr0. before entering either mode, appropriate qsm and qspi registers must be properly initialized. in master mode, the qspi executes a queue of commands defined by control bits in each command ram queue entry. chip-select pins are activated, data is transmitted from transmit ram and received into receive ram. in slave mode, operation proceeds in response to ss pin activation by an external bus master. opera- tion is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. when the qspi is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. although the qspi inherently supports multi-master operation, no special arbitration mechanism is pro- vided. a mode fault flag (modf) indicates a request for spi master arbitration. system software must provide arbitration. note that unlike previous spi systems, mstr is not cleared by a mode fault being set, nor are the qspi pin output drivers disabled. the qspi and associated output drivers must be dis- abled by clearing spe in spcr1. 5.6 sci submodule the sci submodule is used to communicate with external devices through an asynchronous serial bus. the sci is fully compatible with the sci systems found on other motorola mcus, such as the m68hc11 and m68hc05 families. 5.6.1 sci pins there are two unidirectional pins associated with the sci. the sci controls the transmit data (txd) pin when enabled, whereas the receive data (rxd) pin remains a dedicated input pin to the sci. txd is available as a general-purpose i/o pin when the sci transmitter is disabled. when used for i/o, txd can be configured either as input or output, as determined by qsm register ddrqs. table 42 shows sci pins and their functions. 5.6.2 sci registers the sci programming model includes qsm global and pin control registers, and four sci registers. there are two sci control registers, one status register, and one data register. all registers can be read or written at any time by the cpu. changing the value of sci control bits during a transfer operation may disrupt operation. before chang- ing register values, allow the transmitter to complete the current transfer, then disable the receiver and transmitter. status flags in the scsr may be cleared at any time. table 42 sci pins pin names mnemonics mode function receive data rxd receiver disabled receiver enabled not used serial data input to sci transmit data txd transmitter disabled transmitter enabled general-purpose i/o serial data output from sci
mc68ck338 motorola MC68CK338TS/d 73 sccr0 contains a baud rate selection parameter. baud rate must be set before the sci is enabled. the cpu can read and write this register at any time. bits [15:13] ?not implemented scbr[12:0] ?baud rate sci baud rate is programmed by writing a 13-bit value to br. the baud rate is derived from the mcu system clock by a modulus counter. the sci receiver operates asynchronously. an internal clock is necessary to synchronize with an in- coming data stream. the sci baud rate generator produces a receiver sampling clock with a frequency 16 times that of the expected baud rate of the incoming data. the sci determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper po- sitions within the bit period. receiver sampling rate is always 16 times the frequency of the sci baud rate, which is calculated as follows: or where scbr[12:0] is in the range {1, 2, 3, ? 8191} writing a value of zero to scbr[12:0] disables the baud rate generator. table 43 lists the scbr[12:0] settings for standard and maximum baud rates using a 14.44 mhz sys- tem clock. sccr0 sci control register 0 $yffc08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 scbr[12:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 table 43 sci baud rates nominal baud rate actual rate with 14.44 mhz clock scbr[12:0] value 64 64.0 $1b8b 110 110.0 $1006 300 300.0 $05e0 600 600.1 $02f0 1200 1200.1 $0178 2400 2400.3 $00bc 4800 4800.5 $005e 9600 9601.1 $002f 19200 18802.1 $0018 38400 37604.2 $000c 76800 75208.3 $0006 maximum rate 451250.0 $0001 sci baud rate system clock 32 () scbr[12:0] () ----------------------------------------------- - = scbr[12:0] system clock 32 sci baud rate desired -------------------------------------------------------------------------- - =
motorola mc68ck338 74 MC68CK338TS/d sccr1 contains sci configuration parameters. the cpu can read and write this register at any time. the sci can modify rwu in some circumstances. in general, interrupts enabled by these control bits are cleared by reading scsr, then reading (for receiver status bits) or writing (for transmitter status bits) scdr. bit 15 ?not implemented loops ?loop mode 0 = normal sci operation, no looping, feedback path disabled 1 = test sci operation, looping, feedback path enabled loops controls a feedback path on the data serial shifter. when loop mode is enabled, sci transmitter output is fed back into the receive serial shifter. txd is asserted (idle line). both transmitter and receiver must be enabled before entering loop mode. woms ?wired-or mode for sci pins 0 = if configured as an output, txd is a normal cmos output. 1 = if configured as an output, txd is an open-drain output. woms determines whether the txd pin is an open-drain output or a normal cmos output. this bit is used only when txd is an output. if txd is used as a general-purpose input pin, woms has no effect. ilt ?idle-line detect type 0 = short idle-line detect (start count on first one) 1 = long idle-line detect (start count on first one after stop bit(s)) pt ?parity type 0 = even parity 1 = odd parity when parity is enabled, pt determines whether parity is even or odd for both the receiver and the trans- mitter. pe ?parity enable 0 = sci parity disabled 1 = sci parity enabled pe determines whether parity is enabled or disabled for both the receiver and the transmitter. if the re- ceived parity bit is not correct, the sci sets the pf error flag in scsr. when pe is set, the most significant bit (msb) of the data field is used for the parity function, which re- sults in either seven or eight bits of user data, depending on the condition of m bit. table 44 lists the available choices. sccr1 sci control register 1 $yffc0a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 loops woms ilt pt pe m wake tie tcie rie ilie te re rwu sbk reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 44 parity enable data bit selection m pe result 0 0 8 data bits 0 1 7 data bits, 1 parity bit 1 0 9 data bits 1 1 8 data bits, 1 parity bit
mc68ck338 motorola MC68CK338TS/d 75 m ?mode select 0 = sci frame: one start bit, eight data bits, one stop bit (10 bits total) 1 = sci frame: one start bit, nine data bits, one stop bit (11 bits total) wake ?wakeup by address mark 0 = sci receiver awakened by idle-line detection 1 = sci receiver awakened by address mark (last bit set) tie ?transmit interrupt enable 0 = sci tdre interrupts inhibited 1 = sci tdre interrupts enabled tcie ?transmit complete interrupt enable 0 = sci tc interrupts inhibited 1 = sci tc interrupts enabled rie ?receiver interrupt enable 0 = sci rdrf interrupt inhibited 1 = sci rdrf interrupt enabled ilie ?idle-line interrupt enable 0 = sci idle interrupts inhibited 1 = sci idle interrupts enabled te ?transmitter enable 0 = sci transmitter disabled (txd pin may be used as i/o) 1 = sci transmitter enabled (txd pin dedicated to sci transmitter) the transmitter retains control of the txd pin until completion of any character transfer that was in progress when te is cleared. re ?receiver enable 0 = sci receiver disabled (status bits inhibited) 1 = sci receiver enabled rwu ?receiver wakeup 0 = normal receiver operation (received data recognized) 1 = wakeup mode enabled (received data ignored until awakened) setting rwu enables the wakeup function, which allows the sci to ignore received data until awakened by either an idle line or address mark (as determined by wake). when in wakeup mode, the receiver status flags are not set, and interrupts are inhibited. this bit is cleared automatically (returned to normal mode) when the receiver is awakened. sbk ?send break 0 = normal operation 1 = break frame(s) transmitted after completion of current frame sbk provides the ability to transmit a break code from the sci. if the sci is transmitting when sbk is set, it will transmit continuous frames of zeros after it completes the current frame, until sbk is cleared. if sbk is toggled (one to zero in less than one frame interval), the transmitter sends only one or two break frames before reverting to idle line or beginning to send data. scsr sci status register $yffc0c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used tdre tc rdrf raf idle or nf fe pf reset: 1 1 0 0 0 0 0 0 0
motorola mc68ck338 76 MC68CK338TS/d scsr contains flags that show sci operational conditions. these flags can be cleared either by hard- ware or by a special acknowledgment sequence. the sequence consists of scsr read with flags set, followed by scdr read (write in the case of tdre and tc). a long-word read can consecutively access both scsr and scdr. this action clears receive status flag bits that were set at the time of the read, but does not clear tdre or tc flags. if an internal sci signal for setting a status bit comes after the cpu has read the asserted status bits, but before the cpu has written or read register scdr, the newly set status bit is not cleared. scsr must be read again with the bit set. also, scdr must be written or read before the status bit is cleared. reading either byte of scsr causes all 16 bits to be accessed. any status bit already set in either byte will be cleared on a subsequent read or write of register scdr. tdre ?transmit data register empty flag 0 = register tdr still contains data to be sent to the transmit serial shifter. 1 = a new character can now be written to the transmit data register. tdre is set when the byte in the transmit data register is transferred to the transmit serial shifter. if tdre is zero, transfer has not occurred and a write to the transmit data register will overwrite the pre- vious value. new data is not transmitted if the transmit data register is written without first clearing tdre. tc ?transmit complete flag 0 = sci transmitter is busy 1 = sci transmitter is idle tc is set when the transmitter finishes shifting out all data, queued preambles (mark/idle line), or queued breaks (logic zero). the interrupt can be cleared by reading scsr when tc is set and then by writing the transmit data register of scdr. rdrf ?receive data register full flag 0 = receive data register is empty or contains previously read data. 1 = receive data register contains new data. rdrf is set when the content of the receive serial shifter is transferred to the receive data register. if one or more errors are detected in the received word, flag(s) nf, fe, and/or pf are set within the same clock cycle. raf ?receiver active flag 0 = sci receiver is idle 1 = sci receiver is busy raf indicates whether the sci receiver is busy. it is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. raf can be used to reduce collisions in systems with multiple masters. idle ?idle-line detected flag 0 = sci receiver did not detect an idle-line condition. 1 = sci receiver detected an idle-line condition. idle is disabled when rwu in sccr1 is set. idle is set when the sci receiver detects the idle-line condition specified by ilt in sccr1. if cleared, idle will not set again until after rdrf is set. rdrf is set when a break is received, so that a subsequent idle line can be detected. or ?overrun error flag 0 = rdrf is cleared before new data arrives. 1 = rdrf is not cleared before new data arrives. or is set when a new byte is ready to be transferred from the receive serial shifter to the receive data register, and rdrf is still set. data transfer is inhibited until or is cleared. previous data in receive data register remains valid, but data received during overrun condition (including the byte that set or) is lost.
mc68ck338 motorola MC68CK338TS/d 77 nf ?noise error flag 0 = no noise detected on the received data 1 = noise occurred on the received data nf is set when the sci receiver detects noise on a valid start bit, on any data bit, or on a stop bit. it is not set by noise on the idle line or on invalid start bits. each bit is sampled three times. if none of the three samples are the same logic level, the majority value is used for the received data value, and nf is set. nf is not set until an entire frame is received and rdrf is set. fe ?framing error flag 0 = no framing error on the received data. 1 = framing error or break occurred on the received data. fe is set when the sci receiver detects a zero where a stop bit was to have occurred. fe is not set until the entire frame is received and rdrf is set. a break can also cause fe to be set. it is possible to miss a framing error if rxd happens to be at logic level one at the time the stop bit is expected. pf ?parity error flag 0 = no parity error on the received data 1 = parity error occurred on the received data pf is set when the sci receiver detects a parity error. pf is not set until the entire frame is received and rdrf is set. scdr contains two data registers at the same address. the receive data register is a read-only register that contains data received by the sci. the data comes into the receive serial shifter and is transferred to the receive data register. the transmit data register is a write-only register that contains data to be transmitted. the data is first written to the transmit data register, then transferred to the transmit serial shifter, where additional format bits are added before transmission. r[7:0]/t[7:0] contain either the first eight data bits received when scdr is read, or the first eight data bits to be transmitted when scdr is written. r8/t8 are used when the sci is configured for 9-bit operation. when it is configured for 8-bit operation, they have no meaning or effect. scdr sci data register $yffc0e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 r8/t8 r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 reset: 0 0 0 0 0 0 0 u u u u u u u u u
motorola mc68ck338 78 MC68CK338TS/d 6 configurable timer module 6 the configurable timer module 6 (ctm6) belongs to a family of timer modules for the motorola modular microcontroller family. the timer architecture is modular relative to the number of time bases (counter submodules) and channels (action submodules or timer i/o pins) that are included. the ctm6 consists of several submodules which are located on either side of the ctm6 internal sub- module bus (smb). all data and control signals within the ctm6 are passed over this bus. the smb is connected to the outside world via the bus interface unit submodule (biusm), which is connected to the intermodule bus (imb), and subsequently the cpu. this configuration allows the cpu to access the data and control registers in each ctm6 submodule on the smb. four local time base buses tbb[1:4], each 16-bits wide, are used to transfer timing information from counters to action submodules. each ctm6 submodule can be connected to two tbbs. figure 17 shows a block diagram of the ctm6. 6.1 overview the time base bus system connects the four counter submodules to the eleven double-action submod- ules (dasms) and eight single-action submodules (sasm) channels. the bus interface unit submodule (biusm) allows all the ctm6 submodules to communicate to the imb via the submodule bus (smb). the counter prescaler submodule (cpsm) generates six different clock frequencies which can be used by any counter submodule. this submodule is contained within the biusm. the free-running counter submodule (fcsm) has a 16-bit up counter with an associated clock source selector, selectable time-base bus drivers, software writable control registers, software readable status bits, and interrupt logic. one fcsm is contained in the ctm6. the modulus counter submodule (mcsm) is an enhancement of the fcsm. a modulus register gives the additional flexibility of recycling the counter at a count other than 64k clock cycles. three mcsms are contained in the ctm6. the single action submodule (sasm) provides an input capture and an output compare for each of two bidirectional pins. a total of four sasms (eight channels) are contained in the ctm6. the double-action submodule (dasm) provides two 16-bit input captures or two 16-bit output compare functions that can occur automatically without software intervention. eleven dasms are contained in the ctm6. the real-time clock submodule (rtcsm) provides a real time clock function independent of other ctm6 submodules. this time counter is driven by a dedicated low frequency oscillator (32.768 khz) for low power consumption. a parallel port i/o submodule (piosm) handles up to eight input/output pins. each pin of the piosm may be programmed as an input or an output under software control. one piosm is contained in the ctm6. the static ram submodule (ramsm) provides 32 bytes (16 words) of contiguous memory locations and takes the address space of four standard submodules. the ramsm works as a stand-by memory. two ramsms are contained in the ctm6. the standby power switch changes the power source of the rtcsm prescaler, counters, and oscillator, as well as the two ramsms to v rtc when v dd drops below its minimum specified value.
mc68ck338 motorola MC68CK338TS/d 79 figure 17 ctm6 block diagram double action submodule (dasm10) double action submodule (dasm9) double action submodule (dasm8) ctd10 ctd9 ctd8 double action submodule (dasm7) ctd7 double action submodule (dasm6) ctd6 double action submodule (dasm5) ctd5 double action submodule (dasm4) ctd4 cio0 cio1 cio2 cio3 cio4 cio5 port i/o submodule (piosm17a) single action submodule (sasm14a) single action submodule (sasm14b) cts14b cts14a single action submodule (sasm12a) single action submodule (sasm12b) double action submodule (dasm29) double action submodule (dasm28) double action submodule (dasm27) ctd29 ctd28 ctd27 double action submodule (dasm26) ctd26 single action submodule (sasm18a) single action submodule (sasm18b) cts18b cts18a single action submodule (sasm24a) single action submodule (sasm24b) cts24b cts24a modulus counter submodule (mcsm2) load external clock free-running counter submodule (fcsm3) modulus counter submodule (mcsm30) load modulus counter submodule (mcsm31) external clock ctm31l load bus interface unit submodule (biusm) clock prescaler submodule (cpsm) real-time clock submodule (rtcsm16) xrtc exrtc standby power vrtc vssrtcosc vssrtcosc switch sram submodule (ramsm32) sram submodule (ramsm36) time base bus 1 time base bus 2 time base bus 4 time base bus 3 global time base bus a global time base bus b ctm6 block v dd v ddsyn
motorola mc68ck338 80 MC68CK338TS/d 6.2 address map the ctm6 address map occupies 512 bytes. all ctm6 registers are addressable in supervisor space only. table 45 shows the ctm6 register. table 45 ctm6 address map address 15 0 $yff400 1 biusm module configuration register (biumcr) $yff402 biusm test register (biutest) $yff404 biusm time base register (biutbr) $yff406 reserved $yff408 cpsm control register (cpcr) $yff40a cpsm test register (cptr) $yff40c ?yff40e reserved $yff410 mcsm2 status/interrupt/control register (mcsm2sicr) $yff412 mcsm2 counter register (mcsm2cnt) $yff414 mcsm2 modulus latch (mcsm2ml) $yff416 reserved $yff418 fcsm3 status/interrupt/control register (fcsm3sic) $yff41a fcsm3 counter register (fcsm3cnt) $yff41c ?$yff41e reserved $yff420 dasm4 status/interrupt/control register (dasm4sic) $yff422 dasm4 register a (dasm4a) $yff424 dasm4 register b (dasm4b) $yff426 reserved $yff428 dasm5 status/interrupt/control register (dasm5sic) $yff42a dasm5 register a (dasm5a) $yff42c dasm5 register b (dasm5b) $yff42e reserved $yff430 dasm6 status/interrupt/control register (dasm6sic) $yff432 dasm6 register a (dasm6a) $yff434 dasm6 register b (dasm6b) $yff436 reserved $yff438 dasm7 status/interrupt/control register (dasm7sic) $yff43a dasm7 register a (dasm7a) $yff43c dasm7 register b (dasm7b) $yff43e reserved $yff440 dasm8 status/interrupt/control register (dasm8sic) $yff442 dasm8 register a (dasm8a) $yff444 dasm8 register b (dasm8b) $yff446 reserved $yff448 dasm9 status/interrupt/control register (dasm9sic) $yff44a dasm9 register a (dasm9a) $yff44c dasm9 register b (dasm9b) $yff44e reserved
mc68ck338 motorola MC68CK338TS/d 81 $yff450 dasm10 status/interrupt/control register (dasm10sic) $yff452 dasm10 register a (dasm10a) $yff454 dasm10 register b (dasm10b) $yff456 ?$yff45e reserved $yff460 sasm12 status/interrupt/control register a (sic12a) $yff462 sasm12 data register a (s12data) $yff464 sasm12 status/interrupt/control register b (sic12b) $yff466 sasm12 data register b (s12datb) $yff468 ?$yff46e reserved $yff470 sasm14 status/interrupt/control register a (sic14a) $yff472 sasm14 data register a (s14data) $yff474 sasm14 status/interrupt/control register b (sic14b) $yff476 sasm14 data register b (s14datb) $yff478 ?$yff47e reserved $yff480 rtcsm16 status/interrupt/control register (rtc16sic) $yff482 rtcsm16 prescaler register (r16prr) $yff484 rtcsm16 32-bit free-running counter high (r16frch) $yff486 rtcsm16 32-bit free-running counter low (r16frcl) $yff488 piosm17a i/o port register (pio17a) $yff48a ?$yff48e reserved $yff490 sasm18 status/interrupt/control register a (sic18a) $yff492 sasm18 data register a (s18data) $yff494 sasm18 status/interrupt/control register b (sic18b) $yff496 sasm18 data register b (s18datb) $yff498 ?yff4be reserved $yff4c0 sasm24 status/interrupt/control register a (sic24a) $yff4c2 sasm24 data register a (s24data) $yff4c4 sasm24 status/interrupt/control register b (sic24b) $yff4c6 sasm24 data register b (s24datb) $yff4c8 ?$yff4ce reserved $yff4d0 dasm26 status/interrupt/control register (dasm26sic) $yff4d2 dasm26 register a (dasm26a) $yff4d4 dasm26 register b (dasm26b) $yff4d6 reserved $yff4d8 dasm27 status/interrupt/control register (dasm27sic) $yff4da dasm27 register a (dasm27a) $yff4dc dasm27 register b (dasm27b) $yff4de reserved $yff4e0 dasm28 status/interrupt/control register (dasm28sic) $yff4e2 dasm28 register a (dasm28a) $yff4e4 dasm28 register b (dasm28b) $yff4e6 reserved table 45 ctm6 address map (continued) address 15 0
motorola mc68ck338 82 MC68CK338TS/d 6.3 time base bus system the time base bus system is composed of four 16-bit buses: tbb1, tbb2, tbb3 and tbb4. they are arranged so that each ctm6 submodule can be connected to two time base buses. figure 18 shows that ctm6 submodules numbered 1 to m-1 can be connected to tbb3 and tbb4. ctm6 submodules m to n can be connected to tbb1 and tbb2. control bits within each ctm6 submodule allow the soft- ware to connect the submodule to the desired time base bus(es). notes: 1. y = m111, where m is the logic state of the module mapping (mm) bit in the simlcr. $yff4e8 dasm29 status/interrupt/control register (dasm29sic) $yff4ea dasm29 register a (dasm29a) $yff4ec dasm29 register b (dasm29b) $yff4ee reserved $yff4f0 mcsm30 status/interrupt/control register (mcsm30sic) $yff4f2 mcsm30 counter register (mcsm30cnt) $yff4f4 mcsm30 modulus latch (mcsm30ml) $yff4f6 reserved $yff4f8 mcsm31 status/interrupt/control register (mcsm31sic) $yff4fa mcsm31 counter register (mcsm31cnt) $yff4fc mcsm31 modulus latch (mcsm31ml) $yff4fe reserved $yff500 ?$yff51e ramsm32 ram $yff520 ?$yff53e ramsm36 ram $yff540 ?$yff5fe reserved table 45 ctm6 address map (continued) address 15 0
mc68ck338 motorola MC68CK338TS/d 83 figure 18 time base bus configuration as shown in figure 18 , each ctm submodule can access one of two global time base buses. tbb1 and tbb4 are collectively referred to as global time base bus tbba. likewise, tbb2 and tbb3 are col- lectively referred to as global time base bus tbbb. table 46 shows which time base buses are available for each ctm6 submodule. time base buses are used to transfer timing information from counters to action submodules. each ctm6 submodule can either be a clock source module (and drive one or two of the time base buses) or an action submodule (and read and react to the timing information on the time base buses). table 46 ctm6 time base bus allocation global/local time base bus allocation global/local time base bus allocation submodule global bus a global bus b submodule global bus a global bus b mcsm2 tbb4 tbb3 sasm18 tbb1 tbb2 fcsm3 tbb4 tbb3 sasm24 tbb1 tbb2 dasm4 ?10 tbb4 tbb3 dasm26 ?29 tbb1 tbb2 sasm12 ?14 tbb4 tbb3 mcsm30 ?31 tbb1 tbb2 submodule m bus interface unit submodule (biusm) intermodule bus (imb) time base bus 1 (tbb1) time base bus a (tbba) time base bus 3 (tbb3) time base bus 4 (tbb4) submodule bus (smb) submodule n submodule m+1 submodule m-1 submodule 1 submodule 2 time base bus b (tbbb) time base bus 2 (tbb2) ctm tbb block
motorola mc68ck338 84 MC68CK338TS/d the time base buses are precharge/discharge type buses with wired-or capability, so that no hardware damage occurs when several counters are driving the same bus at the same time. 6.4 bus interface unit submodule (biusm) the biusm connects the smb to the imb and allows the ctm6 submodules to communicate with the cpu. the biusm also communicates interrupt requests from the ctm6 submodules to the imb, and transfers the interrupt level, arbitration bit and vector number to the cpu during the interrupt acknowl- edge cycle. 6.4.1 biusm registers the biusm contains a module configuration register, a time base register, and a test register. the biusm register block always occupies the first four register locations in the ctm6 register space and cannot be relocated within the ctm6 structure. all unused bits and reserved address locations return zero when read by the software. writing to unused bits and reserved address locations has no effect. stop ?stop enable the stop bit, while asserted, completely stops operation of the ctm6. the biusm continues to oper- ate to allow the cpu access to submodule registers. the ctm6 remains stopped until reset or until the stop bit is negated by the cpu. 0 = allows operation of the ctm6 1 = stops operation of the ctm6 frz ?freeze assertion response 0 = ignore imb freeze signal 1 = ctm6 stops when imb freeze signal is asserted note some submodules may validate this signal with internal enable bits. bit 13 ?not implemented vect[7:6] ?interrupt vector base number field this bit field selects the interrupt vector base number for the ctm6. of the eight bits necessary for vec- tor number definition, the six least significant bits are programmed by hardware on a submodule basis, while the two remaining bits are provided by vect[7:6]. this places the ctm6 vectors in one of four possible positions in the interrupt vector table. refer to table 47 . biumcr biu module configuration register $yff400 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stop frz 0 vect[7:6] iarb[2:0] 0 0 tbrs1 0 0 0 0 tbrs0 reset: 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 table 47 interrupt vector base number bit field vect7 vect6 resulting vector base number 0 0 $00 0 1 $40 1 0 $80 1 1 $c0
mc68ck338 motorola MC68CK338TS/d 85 iarb[2:0] ?interrupt arbitration field this bit field and the iarb3 bit within each submodule provide 15 different interrupt arbitration numbers that can be used to arbitrate between interrupt requests occurring on the imb with the same interrupt priority level. the iarb field defaults to zero on reset, preventing the module from arbitrating during an iack cycle. if no arbitration takes place during the iack cycle, the siml generates a spurious interrupt, indicating to the system that the interrupt arbitration number has not been initialized. the ctm6 allows two different arbitration numbers to be used by providing each submodule with its own iarb3 bit (which can be set or cleared in software). once iarb[2:0] are assigned in the biusm, they apply to all ctm6 interrupt requests. therefore, ctm6 submodule interrupts can be prioritized with re- quests from other modules at the same interrupt level. iarb[2:0] are cleared by reset. bits[7:6], [4:1] ?not implemented tbrs1, tbrs0 ?time base register bus select bits these bits specify which time base bus is accessed when the time base register (biutbr) is read. re- fer to table 48 . biutest ? biusm test register $yff402 biutest is used during factory testing of the ctm6. accesses to biutest must be made while the mcu is in test mode. biutbr is a read-only register used to read the value present on one of the time base buses. the time base bus being accessed is determined by tbrs1 and tbrs0 in biumcr. writing to biutbr has no effect during normal operation. 6.5 counter prescaler submodule (cpsm) the counter prescaler submodule (cpsm) is a programmable divider system that provides the ctm6 counters with a choice of six clock signals (pclkx) derived from the sixth frequency mcu system clock (f sys ). five of these frequencies are derived from a fixed divider chain. the divide ratio is software se- lectable from a choice of four divide ratios. the cpsm is contained within the biusm. figure 19 shows a block diagram of the cpsm. table 48 time base register bus select bits tbrs1 tbrs0 time base bus 0 0 tbb1 0 1 tbb2 1 0 tbb3 1 1 tbb4 biutbr biusm time base register $yff404 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
motorola mc68ck338 86 MC68CK338TS/d figure 19 cpsm block diagram 6.5.1 cpsm registers the cpsm contains a control register and a test register. all unused bits and reserved address loca- tions return zero when read by the software. writing to unused bits and reserved address locations has no effect. prun ?prescaler running the prun bit is a read/write control bit that allows the software to switch the prescaler counter on and off. this bit allows the counters in various ctm6 submodules to be synchronized. it is cleared by reset. 0 = prescaler is held in reset and is not running 1 = prescaler is running div23 ?divide by 2/divide by 3 the div23 bit is a read/write control bit that selects the division ratio of the first prescaler counter. it may be changed by the software at any time and is cleared by reset. 0 = first prescaler stage divides by two 1 = first prescaler stage divides by three psel[1:0] ?prescaler division ratio select field this bit field selects the division ratio of the programmable prescaler output signal (pclk6). refer to table 49 . cpcr cpsm control register $yff408 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not used prun div23 psel[1:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ctm cpsm block f sys 8-bit pclk2 = pclk3 = pclk4 = pclk5 = pclk6 = first cpsm select pclk1 = ? 2 ? 4 ? 8 ? 16 ? 32 prescaler ? 64 ? 128 ? 256 prun div23 psel1 psel0 cpcr prescaler ? 2 or ? 3 f sys ? 2 f sys ? 4 f sys ? 8 f sys ? 16 f sys ? 32 f sys ? 64 f sys ? 128 f sys ? 256 f sys ? 512 f sys ? 3 f sys ? 6 f sys ? 12 f sys ? 24 f sys ? 48 f sys ? 96 f sys ? 192 f sys ? 384 f sys ? 768 div23 = ? 3 div23 = ? 2
mc68ck338 motorola MC68CK338TS/d 87 cptr ? cpsm test register $yff40a cptr is used during factory testing of the ctm6. accesses to cptr must be made while the mcu is in test mode. 6.6 clock sources for counter submodules one of seven clock sources can be chosen for each counter submodule. five of them are fixed prescaler taps derived from the system clock: ? 2, ? 4, ? 8, ? 16, and ? 32. a sixth prescaler tap is software selectable as the system clock divided by 64, 128, 256, or 512. an alternate prescaler option provides fixed prescaler taps of the system clock divided by 3, 6, 12, 24, and 48. in this case, the software se- lectable tap is the system clock divided by 96, 192, 384, or 768. the seventh selectable clock source is an external pin which may trigger on the rising or falling edge of the input signal. the external input allows a clock frequency to be selected that is not based on the mcu system clock. alternately, the external clock input allows a counter submodule to be used for pulse or event counting. note the external clock inputs for mcsm30 and mcsm31 are tied to the i/o pin ctd5 for dasm5. the external clock inputs for mcsm2 and fcsm3 are tied to the i/o pin ctd27 for dasm27. 6.7 free-running counter submodule (fcsm) the free-running counter submodule (fcsm) has a 16-bit up counter with an associated clock source selector, selectable time-base bus drivers, software writable control registers, software readable status bits, and interrupt logic. when the 16-bit up counter overflows from $ffff to $0000, an optional over- flow interrupt may be generated. software selects which, if any, time-base bus is to be driven by the 16-bit counter. a software control register selects whether the clock input to the counter is one of the taps from the prescaler or an input pin. the polarity of the external input pin is also programmable. one fcsm is contained in the ctm6. figure 20 shows a block diagram of the fcsm. table 49 prescaler division ratio select field prescaler control register bits prescaler division ratio prun div23 psel1 psel0 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6 0xxx000000 1000248163264 10012481632128 10102481632256 10112481632512 11003612244896 110136122448192 111036122448384 111136122448768
motorola mc68ck338 88 MC68CK338TS/d note in order to count, the fcsm requires the cpsm clock signals to be present. on coming out of reset, the fcsm does not count internal or external events until the prescaler in the cpsm starts running (when the software sets the prun bit). this allows all counters in the ctm6 submodules to be synchronized. figure 20 fcsm block diagram 6.7.1 fcsm registers the fcsm contains a status/interrupt/control register and a counter register. all unused bits and re- served address locations return zero when read. writing to unused bits and reserved address locations has no effect. cof ?counter overflow flag this status flag indicates whether or not a counter overflow has occurred. an overflow is defined to be the transition of the counter from $ffff to $0000. if the il field is non-zero, an interrupt request is gen- erated when the cof bit is set. 0 = counter overflow has not occurred 1 = counter overflow has occurred this flag is set only by hardware and cleared only by software or a system reset. to clear the flag, first read the register with cof set to one, then write a zero to the bit. cof is cleared only if no overflow occurs between the read and write operations. fcsm3sic fcsm status/interrupt/control register $yff418 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cof il[2:0] iarb3 0 drva drvb in 0 0 0 0 clk[2:0] reset: 0 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 ctm fcsm block 16-bit up counter il2 il1 il0 iarb3 cof edge time base buses il1 interrupt clock in clk1 clk0 clk2 overflow bus control register bits control register bits drva drvb control register bits 6 clocks (pclkx) from prescaler submodule bus control select select detect tbba tbbb input pin ctmc
mc68ck338 motorola MC68CK338TS/d 89 il[2:0] ?interrupt level setting il[2:0] to a non-zero value causes the fcsm to request an interrupt of the selected level when the cof bit sets. if il[2:0] = %000, no interrupt will be requested when cof sets. these bits can be read or written at any time and are cleared by reset. iarb3 ?interrupt arbitration bit 3 this bit works in conjunction with iarb[2:0] in the biumcr. each module that generates interrupt re- quests on the imb must have a unique value in the arbitration field. this interrupt arbitration identifica- tion number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority. the iarb3 bit is cleared by reset. refer to 6.4.1 biusm registers for more information on iarb[2:0]. drv[a:b] ?drive time base bus this bit field contains read/write bits that control the connection of the fcsm to the time base buses a and b. these bits are cleared by reset. refer to table 52 . warning two time base buses should not be driven at the same time. in ?input pin status bit this read-only status bit reflects the logic state of the fcsm input pin. writing to this bit has no effect, nor does reset. note the clock input of fcsm3 is internally connected to i/o pin ctd27 of dasm27 and will read the state of that pin. clk[2:0] ?counter clock select these read/write control bits select one of six internal clock signals (pclk[1:6]) or one of two external conditions on the external clock input pin. maximum frequency of the external clock signals is f sys /4. refer to table 54 . table 50 drive time base bus field drva drvb bus selected 0 0 no time base bus driven 0 1 time base bus b is driven 1 0 time base bus a is driven 1 1 both time base buses a and b are driven table 51 counter clock select field clk2 clk1 clk0 free-running counter clock source 000 pclk1 (f sys ? 2 or f sys ? 3) 001 pclk2 (f sys ? 4 or f sys ? 6) 010 pclk3 (f sys ? 8 or f sys ? 12) 011 pclk4 (f sys ? 16 or f sys ? 24) 100 pclk5 (f sys ? 3 2 or f sys ? 48) 101 pclk6 (f sys ? 64 or f sys ? 768) 1 1 0 external clock input, falling edge 1 1 1 external clock input, rising edge
motorola mc68ck338 90 MC68CK338TS/d the fcsm counter register is a read/write register. a read returns the current value of the counter. a write loads the counter with the specified value. the counter then begins incrementing from this new value. 6.8 modulus counter submodule (mcsm) the modulus counter submodule (mcsm) is an enhancement of the fcsm. the mcsm contains a 16- bit modulus latch, a 16-bit loadable up-counter, counter loading logic, a clock selector, a time base bus driver, and an interrupt interface. a modulus latch gives the additional flexibility of recycling the counter at a count other than 64-kbyte clock cycles. the state of the modulus latch is transferred to the counter when an overflow occurs or when a user-specified edge transition occurs on an external input pin. in addition, a write to the modulus counter simultaneously loads both the counter and the modulus latch with the specified value. the counter then begins incrementing from this new value. three mcsms are contained in the ctm6. figure 21 shows a block diagram of the mcsm. note in order to count, the mcsm requires the cpsm clock signals to be present. on coming out of reset, the mcsm does not count internal or external events until the prescaler in the cpsm starts running (when the software sets the prun bit). this allows all counters in the ctm6 submodules to be synchronized. figure 21 mcsm block diagram fcsm3cnt fcsm counter register $yff41a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 interrupt control clock input pin ctmc ctm mcsm block 16-bit up counter il2 il1 il0 iarb3 cof edge time base buses il1 clock in2 clk1 clk0 clk2 overflow bus control register bit control register bits 6 clocks (pclkx) from prescaler submodule bus select select detect modulus control modulus register control register bits edgen edgep edge modulus load detect input pin ctml in1 control register bits write both drva drvb control register bits tbba tbbb modulus control register bit load input pin ctml
mc68ck338 motorola MC68CK338TS/d 91 6.8.1 mcsm registers the mcsm contains a status/interrupt/control register, a counter, and a modulus latch. all unused bits and reserved address locations return zero when read. writing to unused bits and reserved address locations has no effect. the ctm6 contains three mcsms, each with its own set of registers. cof ?counter overflow flag this status flag indicates whether or not a counter overflow has occurred. an overflow of the mcsm counter is defined to be the transition of the counter from $ffff to $xxxx, where $xxxx is the value con- tained in the modulus latch. if the il[2:0] field is non-zero, an interrupt request is generated when the cof bit is set. 0 = counter overflow has not occurred 1 = counter overflow has occurred this flag is set only by hardware and cleared only by software or by a system reset. to clear the flag, the software must first read the register with cof set to one, then write a zero to the bit. cof is cleared only if no overflow occurs between the read and write operations. il[2:0] ?interrupt level setting il[2:0] to a non-zero value causes the mcsm to request an interrupt of the selected level when the cof bit sets. if il[2:0] = %000, no interrupt will be requested when cof sets. these bits can be read or written at any time and are cleared by reset. iarb3 ?interrupt arbitration bit 3 this bit works in conjunction with iarb[2:0] in the biumcr. each module that generates interrupt re- quests on the imb must have a unique value in the arbitration field. this interrupt arbitration identifica- tion number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority. the iarb3 bit is cleared by reset. refer to 6.4.1 biusm registers for more information on iarb[2:0]. drv[a:b] ?drive time base bus this bit field contains read/write bits that control the connection of the mcsm to time base buses a and b. these bits are cleared by reset. refer to table 52 . warning two time base buses should not be driven at the same time. mcsm2sic mcsm2 status/interrupt/control register $yff410 mcsm30sic mcsm30 status/interrupt/control register $yff4f0 mcsm31sic mcsm31 status/interrupt/control register $yff4f8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cof il[2:0] iarb3 0 drva drvb in2 in1 edgen edgep 0 clk[2:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 52 drive time base bus field drva drvb bus selected 0 0 no time base bus is driven 0 1 time base bus b is driven 1 0 time base bus a is driven 1 1 both time base buses a and b are driven
motorola mc68ck338 92 MC68CK338TS/d in2 ?clock input pin status this read-only status bit reflects the logic state of the clock input pin. writing to this bit has no effect, nor does reset. note the clock input of mcsm2 is internally connected to i/o pin ctd27 for dasm27 and will read the state of that pin. the clock inputs of mcsm30 and mcsm31 are internally connected to i/o pin ctd5 for dasm5 and will read the state of that pin. in1 ?modulus load input pin status this read-only status bit reflects the logic state of the modulus load input pin. writing to this bit has no effect, nor does reset. note the load input of mcsm2 is internally connected to i/o pin ctd29 for dasm29 and will read the state of that pin. the load input of mcsm30 is internally connected to i/o pin ctd4 for dasm4 and will read the state of that pin. the load input of mcsm31 is available externally on the ctm31l pin. edgen, edgep ?modulus load edge sensitivity bits these read/write control bits select the sensitivity of the edge detection circuitry on the modulus load pin ctml. refer to table 53 . clk[2:0] ?counter clock select these read/write control bits select one of six internal clock signals (pclk[1:6]) or one of two external conditions on the external clock input pin (rising edge or falling edge). the maximum frequency of the external clock signals is f sys /4. refer to table 54 . table 53 modulus load edge sensitivity edgen edgep in1 edge detector sensitivity 0 0 none 0 1 positive edge only 1 0 negative edge only 1 1 positive and negative edge table 54 counter clock select clk2 clk1 clk0 free-running counter clock source 000 pclk1 (f sys ? 2 or f sys ? 3) 001 pclk2 (f sys ? 4 or f sys ? 6) 010 pclk3 (f sys ? 8 or f sys ? 12) 011 pclk4 (f sys ? 16 or f sys ? 24) 100 pclk5 (f sys ? 3 2 or f sys ? 48) 101 pclk6 (f sys ? 64 or f sys ? 768) 1 1 0 external clock input, falling edge 1 1 1 external clock input, rising edge
mc68ck338 motorola MC68CK338TS/d 93 note the clock input of mcsm2 is internally connected to i/o pin ctd27 for dasm27 and will read the state of that pin. the clock inputs of mcsm30 and mcsm31 are internally connected to i/o pin ctd5 for dasm5 and will read the state of that pin. the mcsm counter register is a read/write register. a read returns the current value of the counter. a write simultaneously loads both the counter and the mcsm modulus latch with the specified value. the counter then begins incrementing from this new value. the mcsm modulus latch register is a read/write register. a read returns the current value of the latch. a write pre-loads the latch with a new value that the modulus counter will begin counting from when the next load condition occurs. 6.9 single action submodule (sasm) the single action submodule (sasm) provides two identical channels, each having its own input/output pin, but sharing the same interrupt logic, priority level, and arbitration number. each channel can be configured independently to perform either input capture or output compare. table 55 shows the differ- ent operational modes. notes: 1. when a channel is operating in ic mode, the in bit in the sic register reflects the logic state of the corresponding input pin (after being schmitt triggered and synchronized). 2. when a channel is operating in oc, oct, or op mode, the in bit in the sic register reflects the logic state of the output of the output flip-flop. mcsm2cnt mcsm2 counter register $yff412 mcsm30cnt mcsm30 counter register $yff4f2 mcsm31cnt mcsm31 counter register $yff4fa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mcsm2ml mcsm2 modulus latch $yff414 mcsm30ml mcsm30 modulus latch $yff4f4 mcsm31ml mcsm31 modulus latch $yff4fc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 55 sasm operational modes mode function ic 1 input capture either on a rising or falling edge or as a read-only input port oc 2 output compare oct 2 output compare and toggle op 2 output port
motorola mc68ck338 94 MC68CK338TS/d note all of the functions associated with one pin are called a sasm channel. the sasm can perform a single timing action (input capture or output compare) before software inter- vention is required. each channel includes a 16-bit comparator and one 16-bit register for saving an in- put capture value or for holding an output compare value. the input edge detector associated with each pin is programmable to cause the capture function to occur on the rising or falling edge. the output flip flop can be set to either toggle when an output compare occurs or to transfer a software-provided bit value to the output pin. in either input capture or output compare mode, each channel can be pro- grammed to generate an interrupt. one of the two incoming time-base buses may be selected for each channel. each channel can also work as a simple i/o pin. a total of four sasms (eight channels) are contained in the ctm6. figure 22 shows a block diagram of the sasm. figure 22 sasm block diagram 6.9.1 sasm registers the sasm contains two status/interrupt/control registers (a and b) and two data registers (a and b). all unused bits and reserved address locations return zero when read. writing to unused bits and reserved address locations has no effect. the ctm6 contains four sasms, each with its own set of reg- isters. sic12a, sic14a sasm status/interrupt/control register a $yff460, $yff470 sic18a, sic24a sasm status/interrupt/control register a $yff490, $yff4c0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 flag il[2:0] iarb3 ien 0 bsl in 0 force edout 0 0 mode[1:0] reset: 0 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 i/o pin i/o pin ctm sasm block single action channel a ctm time base buses submodule bus single action channel b interrupt control il2 il0 iarb3 flag ien il1 flag
mc68ck338 motorola MC68CK338TS/d 95 sica and sicb contain the control and status bits for sasm channels a and b, respectively. sica also contains the il[2:0] interrupt level field and iarb3 interrupt arbitration bit 3 for both sasm channels a and b. flag ?event flag flag indicates whether or not an input capture or output compare event has occurred. if the il[2:0] field is non-zero, and ien is set, an interrupt request is generated when flag is set. 0 = an input capture or output compare event has not occurred 1 = an input capture or output compare event has occurred table 56 shows the event flag status during different modes. flag is set only by hardware and cleared only by software or by a system reset.to clear this bit, first read the register with flag set to one, then write a zero to the bit. note the flag clearing mechanism works only if no flag setting event occurs between the read and write operations. if a flag setting event occurs between the read and write operations, the flag bit will not cleared. il[2:0] ?interrupt level setting ip[2:0] to a non-zero value causes the sasm to request an interrupt when the flag bit sets. if il[2:0] = %000, no interrupts will be requested when flag sets. note this field affects both sasm channels, not just channel a. iarb3 ?interrupt arbitration bit 3 this bit works in conjunction with iarb[2:0] in the biumcr. each module that generates interrupt re- quests on the imb must have a unique value in the arbitration field. this interrupt arbitration identifica- tion number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority. the iarb3 bit is cleared by reset. refer to 6.4.1 biusm registers for more information on iarb[2:0]. sic12b, sic14b sasm status/interrupt/control register b $yff464, $yff474 sic18b, sic24b sasm status/interrupt/control register b $yff494, $yff4c4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 flag 0 0 0 0 ien 0 bsl in 0 force edout 0 0 mode[1:0] reset: 0 0 0 0 0 0 0 0 u 0 0 0 0 0 0 0 table 56 event flag status conditions mode status description ic if a subsequent input capture event occurs while flag is set, the new value is latched and flag remains set. oc if a subsequent output compare event occurs while flag is set, the compare occurs normally and flag remains set. oct if a subsequent output compare event occurs while flag is set, the output signal toggles nor- mally and flag remains set. op if a subsequent internal compare event occurs while flag is set, the compare occurs normally and flag remains set.
motorola mc68ck338 96 MC68CK338TS/d note this bit field affects both sasm channels, not just channel a. ien ?interrupt enable this control bit enables interrupts when flag is set and the il[2:0] field is non-zero. 0 = interrupts disabled 1 = interrupts enabled bsl ?time base bus select this control bit selects the time base bus connected to the sasm. 0 = time base bus a selected 1 = time base bus b selected in ?input pin status in input mode (ic), the in bit reflects the logic state present on the corresponding input pin after being schmitt triggered and synchronized. in the output modes (oc, oct and op), the in bit value reflects the state of the output flip-flop. the in bit is a read-only bit. reset has no effect on this bit. note the input of sasm12a is internally connected to i/o pin ctd29 and will read the state of that pin. the input of sasm12b is internally connected to i/o pin ctd26 and will read the state of that pin. force ?force compare control in the ic and op modes, force is not used and writing to it has no effect. in the oc and oct modes, force is used by software to cause the output flip-flop (and the output pin) to behave as though an output compare had occurred. in oc and oct mode, setting force caus- es the value of edout to be transferred to the output of the output flip-flop. internal synchronization ensures that the correct level appears on the output pin when a new value is written to edout and force is set at the same time. 0 = no action 1 = force output flip-flop to behave as if an output compare has occurred force is cleared by reset and always reads as zero. note flag is not affected by the use of the force bit. edout ?edge detect and output level in ic mode, edout is used to select the edge that triggers the input capture circuitry. 0 = input capture on falling edge 1 = input capture on rising edge in oc and oct mode, the edout bit is used to latch the value to be output to the pin on the next output compare match or when the force is set. internal synchronization ensures that the correct level ap- pears on the output pin when a new value is written to edout and force is set at the same time. reading edout returns the previous value written. in op mode, the value of edout is output to the corresponding pin. reading edout returns the pre- vious value written. mode[1:0] ?sasm operating mode this bit field selects the mode of operation for the sasm channel. refer to table 57 .
mc68ck338 motorola MC68CK338TS/d 97 sdata and sdatb are the data registers associated with sasm channels a and b, respectively. in ic mode, sdata and sdatb contain the last captured value. in the oc, oct and op modes, sdata and sdatb are loaded with the value of the next output compare. 6.10 double-action submodule (dasm) the double-action submodule (dasm) provides two 16-bit input capture or two 16-bit output compare functions that can occur automatically without software intervention. the input edge detector is pro- grammable to cause the capture function to occur on user-specified edges. the output flip flop is set by one of the output compare signals and reset by the other one. the dasm input capture and the output compare modes may optionally generate interrupts. software determines which of the two incoming time-base buses is used for input captures or output compares. six operating modes allow software to use dasm input capture and output compare functions to per- form pulse-width measurement, period measurement, single pulse generation, and continuous pulse width modulation, as well as standard input capture and output compare. the dasm can also work as a single i/o pin. dasm operation is determined by the mode select bit field mode[3:0] in the dasm status/interrupt/control (dasmsic) register. table 58 shows the different dasm modes of operation. table 57 sasm operating mode select mode1 mode2 sasm channel operating mode 0 0 input capture (ic) 0 1 output port (op) 1 0 output compare (oc) 1 1 output compare and toggle (oct) s12data, s14data sasm data register a $yff462, $yff472 s18data, s24data sasm data register a $yff492, $yff4c2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: u u u u u u u u u u u u u u u u s12datb, s14datb sasm data register b $yff464, $yff474 s18datb, s24datb sasm data register b $yff494, $yff4c4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: u u u u u u u u u u u u u u u u
motorola mc68ck338 98 MC68CK338TS/d the dasm is composed of two timing channels (a and b), an output flip-flop, an input edge detector, some control logic and an interrupt interface. all control and status bits are contained in the dasmsic register. channel a consists of one 16-bit data register and one 16-bit comparator. to the user, channel b also appears to consist of one 16-bit data register and one 16-bit comparator, though internally, channel b has two data registers (b1 and b2). the operating mode determines which register is accessed by the software. refer to table 59 . register contents are always transferred automatically at the correct time so that the minimum pulse (measurement or generation) is just one time base bus count. the a and b data registers are always read/write registers, accessible via the ctm6 submodule bus. eleven dasms are contained in the ctm6. figure 23 shows a block diagram of the dasm. table 58 dasm modes of operation mode description of mode dis disabled ?i/o pin is placed in a high impedance state ipwm input pulse width measurement ?capture on leading and the trailing edges of an input pulse ipm input period measurement ?capture on two consecutive rising or falling edges of an input pulse ic input capture ?capture on user-specified edge ocb output compare, flag set on channel b match ?generate leading and trailing edges of an output pulse and set flag on second edge ocab output compare, flag set on channels a and b match ?generate leading and trailing edges of an output pulse and set flag on both edges opwm output pulse width modulation ?generate continuous pwm output with 7, 9, 11, 12, 13, 14, 15, or 16 bits of resolution table 59 channel b data register access mode data register ipwm, ipm, ic registers a and b2 are used to hold the captured values. in these modes, the b1 register is used as a temporary latch for channel b. oca, ocab registers a and b2 are used to define the output pulse. register b1 is not used in these modes. opwm registers a and b1 are used as primary registers and hidden register b2 is used as a double buffer for channel b.
mc68ck338 motorola MC68CK338TS/d 99 figure 23 dasm block diagram 6.10.1 dasm registers the dasm contains one status/interrupt/control register and two data registers (a and b). all unused bits and reserved address locations return zero when read. writing to unused bits and reserved address locations has no effect. the ctm6 contains 11 dasms, each with its own set of registers. dasm4sic, dasm5sic dasm status/interrupt/control register $yff420, $yff428 dasm6sic, dasm7sic dasm status/interrupt/control register $yff430, $yff438 dasm8sic, dasm9sic dasm status/interrupt/control register $yff440, $yff448 dasm10sic, dasm26sic dasm status/interrupt/control register $yff450, $yff4d0 dasm27sic, dasm28sic dasm status/interrupt/control register $yff4d8, $yff4e0 dasm29sic dasm status/interrupt/control register $yff4e8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 flag il[2:0] iarb3 0 wor bsl in forca forcb edpol mode[3:0] reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 output buffer interrupt control edge detect ctm dasm block 16-bit comparator a il2 il0 iarb3 flag 2 time base buses bus control register bits control register bits in forcb submodule bus select output flip-flop forca i/o pin 16-bit register a bsl mode3 mode2 il1 tbbb tbba 16-bit register b1 16-bit register b2 mode1 mode0 16-bit comparator b wor edpol register b
motorola mc68ck338 100 MC68CK338TS/d flag ?event flag this status bit indicates whether or not an input capture or output compare event has occurred. if the il[2:0] field is non-zero, an interrupt request is generated when flag is set. 0 = an input capture or output compare event has not occurred 1 = an input capture or output compare event has occurred table 56 shows the event flag status during different modes. flag is set only by hardware and cleared by software or by a system reset. to clear the bit, first read the register with flag set to one, then write a zero to the bit. placing the dasm in dis mode will also clear the flag. note the flag clearing mechanism works only if no flag setting event occurs between the read and write operations. if a flag setting event occurs between the read and write operations, the flag bit will not be cleared. il[2:0] ?interrupt level setting il[2:0] to a non-zero value causes the dasm to request an interrupt when the flag bit sets. if il[2:0] = %000, no interrupt will be requested when flag sets. iarb3 ?interrupt arbitration bit 3 this bit works in conjunction with iarb[2:0] in the biumcr. each module that generates interrupt re- quests on the imb must have a unique value in the arbitration field. this interrupt arbitration identifica- tion number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority. the iarb3 bit is cleared by reset. refer to 6.4.1 biusm registers for more information on iarb[2:0]. wor ?wired-or mode in the dis, ipwm, ipm and ic modes, wor is not used. reading this bit returns the value that was previously written. in the ocb, ocab and opwm modes, wor selects whether the output buffer is configured for normal or open drain operation. 0 = output buffer operates in normal mode 1 = output buffer operates in open drain mode bsl ?bus select this bit selects the time base bus connected to the dasm. 0 = dasm is connected to time base bus a. 1 = dasm is connected to time base bus b. table 60 event flag status conditions mode status description dis flag bit is cleared ipwm flag bit is set each time there is a capture on channel a ipm flag bit is set each time there is a capture on channel a, except for the first time ic flag bit is set each time there is a capture on channel a ocb flag bit is set each time there is a successful comparison on channel b ocab flag bit is set each time there is a successful comparison on either channel a or b opwm flag bit is set each time there is a successful comparison on channel a
mc68ck338 motorola MC68CK338TS/d 101 in ?input pin status in the dis, ipwm, ipm and ic modes, this read-only status bit reflects the logic level on the input pin. in the ocb, ocab and opwm modes, reading this bit returns the value latched on the output flip-flop, after edpol polarity selection. writing to this bit has no effect. forca ?force a in the ocb, ocab and opwm modes, forca allows software to force the output flip-flop to behave as if a successful comparison had occurred on channel a (except that the flag bit is not set). writing a one to forca sets the output flip-flop; writing a zero has no effect. in the dis, ipwm, ipm and ic modes, forca is not used and writing to it has no effect. forca is cleared by reset, and always reads as zero. note writing a one to both forca and forcb simultaneously resets the output flip- flop. forcb ?force b in the ocb, ocab and opwm modes, forcb allows software to force the output flip-flop to behave as if a successful comparison had occurred on channel b (except that the flag bit is not set). writing a one to forcb sets the output flip-flop, writing a zero has no effect. in the dis, ipwm, ipm and ic modes, forcb is not used and writing to it has no effect. forcb is cleared by reset, and always reads as zero. note writing a one to both forca and forcb simultaneously resets the output flip- flop. edpol ?edge polarity edpol selects different options depending on the dasm operating mode. refer to table 61 . mode[3:0] ?dasm mode select this bit field selects the operating mode of the dasm. refer to table 62 . table 61 edge polarity mode edpol function dis x edpol is not used in dis mode ipwm 0 channel a captures on a rising edge channel b captures on a falling edge 1 channel a captures on a falling edge channel b captures on a rising edge ipm, ic 0 channel a captures on a rising edge 1 channel a captures on a falling edge ocb, ocab, opwm 0 a compare on channel a sets the output pin to logic one a compare on channel b clears the output pin to logic zero 1 a compare on channel a clears the output pin to logic zero a compare on channel b sets the output pin to logic one
motorola mc68ck338 102 MC68CK338TS/d note to avoid spurious interrupts, dasm interrupts should be disabled before changing the operating mode. dasma is the data register associated with channel a. table 63 shows how the dasma is used with the different operating modes. table 62 dasm mode select field mode[3:0] bits of resolution time base bits ignored dasm operating mode 0000 dis ?disabled 0001 16 ipwm ?input pulse width measurement 0010 16 ipm ?input measurement period 0011 16 ic ?input capture 0100 16 ocb ?output compare, flag on b compare 0101 16 ocab ?output compare, flag on a and b compare 011x not used 1000 16 opwm ?output pulse-width modulation 1001 15 15 opwm ?output pulse-width modulation 1010 14 [15:14] opwm ?output pulse-width modulation 1011 13 [15:13] opwm ?output pulse-width modulation 1100 12 [15:12] opwm ?output pulse-width modulation 1101 11 [15:11] opwm ?output pulse-width modulation 1110 9 [15:9] opwm ?output pulse-width modulation 1111 7 [15:7] opwm ?output pulse-width modulation dasm4a, dasm5a dasm data register a $yff422, $yff42a dasm6a, dasm7a dasm data register a $yff432, $yff43a dasm8a, dasm9a ? dasm data register a $yff442, $yff44a dasm10a, dasm26a dasm data register a $yff452, $yff4d2 dasm27a, dasm28a dasm data register a $yff4da, $yff4e2 dasm29a dasm data register a $yff4ea 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: u u u u u u u u u u u u u u u u
mc68ck338 motorola MC68CK338TS/d 103 dasmb is the data register associated with channel b. table 64 shows how dasmb is used with the different operating modes. depending on the mode selected, software access is to register b1 or reg- ister b2. table 63 dasma operations mode dasma operation dis dasma can be accessed to prepare a value for a subsequent mode selection ipwm dasma contains the captured value corresponding to the trailing edge of the measured pulse ipm dasma contains the captured value corresponding to the most recently detected user-specified rising or falling edge ic dasma contains the captured value corresponding to the most recently detected user-specified rising or falling edge ocb dasma is loaded with the value corresponding to the leading edge of the pulse to be generated. writing to dasma in the ocb and ocab modes also enables the corresponding channel a com- parator until the next successful comparison. ocab dasma is loaded with the value corresponding to the leading edge of the pulse to be generated. writing to dasma in the ocb and ocab modes also enables the corresponding channel a com- parator until the next successful comparison. opwm dasma is loaded with the value corresponding to the leading edge of the pwm pulse to be gen- erated. dasm4b, dasm5b dasm data register b $yff424, $yff42c dasm6b, dasm7b dasm data register b $yff434, $yff43c dasm8b, dasm9b dasm data register b $yff444, $yff44c dasm10b, dasm26b dasm data register b $yff454, $yff4d4 dasm27b, dasm28b dasm data register b $yff4dc, $yff4e4 dasm29b dasm data register b $yff4ec 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: u u u u u u u u u u u u u u u u
motorola mc68ck338 104 MC68CK338TS/d 6.11 real-time clock submodule (rtcsm) with low-power oscillator the real -ime clock submodule provides a real-time clock independent of other ctm6 submodules. this time counter is driven by a dedicated low frequency oscillator (32.768 khz) for low power consumption. the rtcsm contains a 15-bit prescaler and a 32-bit free-running counter, from which seconds, min- utes, hours and days can be determined. the rtcsm can also generate interrupts at one second intervals. the low-power oscillator, prescaler, and counter portions of the rtcsm may be sustained by a separate power supply (v rtc ) for battery backup when v dd is off. the rtcsm and the low-power oscillator can be disabled for minimum power consumption on v rtc when v dd is powered off. this is useful for maximizing the shelf life of the standby battery. refer to 6.14 rtcsm and ramsm standby operation for more information. one rtcsm is contained in the ctm6. figure 24 shows a block diagram of the rtcsm. table 64 dasmb operations mode dasmb operation dis dasmb can be accessed to prepare a value for a subsequent mode selection. in this mode, register b1 is accessed in order to prepare a value for the opwm mode. unused register b2 is hidden and cannot be read, but is written with the same value when register b1 is written. ipwm dasmb contains the captured value corresponding to the trailing edge of the measured pulse. in this mode, register b2 is accessed. buffer register b1 is hidden and cannot be accessed. ipm dasmb contains the captured value corresponding to the most recently detected user-specified rising or falling edge. in this mode, register b2 is accessed. buffer register b1 is hidden and cannot be accessed. ic dasmb contains the captured value corresponding to the most recently detected user-specified rising or falling edge. in this mode, register b2 is accessed. buffer register b1 is hidden and cannot be accessed. ocb dasmb is loaded with the value corresponding to the trailing edge of the pulse to be generated. writing to dasmb in the ocb and ocab modes also enables the corresponding channel b comparator until the next successful comparison. in this mode, register b2 is accessed. buffer register b1 is hidden and cannot be accessed. ocab dasmb is loaded with the value corresponding to the trailing edge of the pulse to be generated. writing to dasmb in the ocb and ocab modes also enables the corresponding channel b comparator until the next successful comparison. in this mode, register b2 is accessed. buffer register b1 is hidden and cannot be accessed. opwm dasmb is loaded with the value corresponding to the trailing edge of the pwm pulse to be generated. in this mode, register b1 is accessed. buffer register b2 is hidden and cannot be accessed
mc68ck338 motorola MC68CK338TS/d 105 figure 24 rtcsm block diagram 6.11.1 rtcsm registers the rtcsm contains one status/interrupt/control register, one 15-bit prescaler register and two 32-bit free-running counter registers (high and low). all unused bits and reserved address locations return zero when read. writing to unused bits and reserved address locations has no effect. tickf ?1 hz clock tick flag tickf is set each time the 32-bit free-running counter is incremented. software can clear tickf by reading the bit as a one, then writing a zero to it. if the il[2:0] field is non-zero, an interrupt request is generated when tickf is set. tickf is not affected by reset. rtc16sic rtcsm status/interrupt/control register $yff480 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tickf il[2:0] iarb3 0 wen en not used reset: u 0 0 0 0 0 0 u 0 0 0 0 0 0 0 0 ctm rtc block interrupt submodule bus 15-bit prescaler 15-bit buffer flag 32-bit free-running 32-bit free-running counter counter buffer prescaler logic (1 h z ) interrupt level control logic arb3 wen en write enable enable status, interrupt, and control register bits 1 h z extal xtal low power oscillator 32.768 khz 10 pf 1 1 pf 1 10 k w 1. resistance and capacitance based on a test circuit constructed with a daishinku dmx-38 32.768 khz crystal. specific components must be based on crystal type. contact crystal vendor for exact circuit. notes:
motorola mc68ck338 106 MC68CK338TS/d note tickf is only cleared if the 32-bit free-running counter does not increment be- tween reading rtc16sic with tickf set to one and then writing tickf to zero. il[2:0] ?interrupt level field setting il[2:0] to a non-zero value causes the rtcsm to request an interrupt of the selected level when the tickf bit sets. if il[2:0] = %000, no interrupt will be requested when tickf sets. iarb3 ?interrupt arbitration bit 3 this bit works in conjunction with iarb[2:0] in the biumcr. each module that generates interrupt re- quests on the imb must have a unique value in the arbitration field. this interrupt arbitration identifica- tion number is used to arbitrate for the imb when modules generate simultaneous interrupts of the same priority. the iarb3 bit is cleared by reset. refer to 6.4.1 biusm registers for more information on iarb[2:0]. wen ?write enable control this bit allows the 15-bit prescaler and the 32-bit free-running counter to be updated. normally, these are read-only registers. regular write operations have no effect. when the wen bit is written to one, it sets a latch that allows the 15-bit prescaler and the 32-bit free-running counter to be written. the latch is automatically reset when the prescaler is written. to write a new value to the complete counter chain: ?write a one to the wen bit. ?execute a long-word write to the 32-bit free-running counter high (r16frch) register. ?execute a word write to the 15-bit prescaler (r16prr) register. wen cannot be written to one again until the writes to update the prescaler and free-running counter have been completed. the wen bit always reads as zero. en ?rtcsm enable this bit selects whether the rtcsm is running or not. 0 = rtcsm is not running 1 = rtcsm is running the en bit is not affected by reset. if the rtcsm is not to be used, it is recommended that en be cleared as soon as the mcu comes out of reset. r16prr contains the synchronized value of the 15-bit prescaler or the value to be loaded into the 15- bit prescaler. note when the rtcsm is disabled, writing to the 15-bit prescaler and 32-bit free- running counter may give unpredictable results. r16prr rtcsm prescaler register $yff482 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: u u u u u u u u u u u u u u u 0
mc68ck338 motorola MC68CK338TS/d 107 r16frch contains the synchronized high word value of the 32-bit free-running counter or the value to be loaded into the high word 32-bit free-running counter. note when the rtcsm is disabled, writing to the 15-bit prescaler and 32-bit free-run- ning counter may give unpredictable results. r16frcl contains the synchronized low word value of the 32-bit free-running counter or the value to be loaded into the low word 32-bit free-running counter. note when the rtcsm is disabled, writing to the 15-bit prescaler and 32-bit free-run- ning counter may give unpredictable results. 6.12 parallel port i/o submodule (piosm) the port i/o submodule (piosm) provides i/o capability independent of other ctm6 modules. the piosm handles up to eight input/output pins. one piosm is contained in the ctm6. figure 25 shows a block diagram of the piosm. figure 25 piosm block diagram r16frch rtcsm free-running counter high register $yff484 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: u u u u u u u u u u u u u u u u r16frcl rtcsm free-running counter low register $yff486 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset: u u u u u u u u u u u u u u u u ctm piosm block output data bit submodule bus i/o pin output data data direction register register input output driver input data bit
motorola mc68ck338 108 MC68CK338TS/d 6.12.1 piosm register the piosm control register is composed of two 8-bit registers. the upper eight bits contain the data register and the lower eight bits contain the data direction register. each piosm pin may be pro- grammed as an input or an output under software control. the data direction register controls whether the corresponding pins are inputs or outputs. the piosm data register can be read or written by the processor. for pins programmed as outputs, a read of the data register actually reads the value of the output data latch and not the i/o pin. ctio[7:6] are not bonded to pins on the mc68338. when one of these signals is configured as an input, a read of the corresponding data bit always returns a zero. when one of these signals is configured as an output, a read of the corresponding data bit returns the value stored in the output data latch. note care should be taken when a single word write cycle is used to modify the data reg- ister and data direction register of the piosm. undesired glitches can occur on pins that change from inputs to outputs and vice versa. to avoid this, first use a byte write cycle to modify the data register then use another byte write cycle to modify the data direction register. 6.13 static ram submodule (ramsm) the static ram submodule (ramsm) provides 32 bytes (16 words) of contiguous memory locations and is not relocatable. it is especially useful for storage of variables and system parameters that must be maintained when the rest of the mcu is powered down. data can be read or written in bytes, words, or long words. ramsm locations are not affected by reset. the ctm6 has two ramsms. table 65 shows the ramsm address locations. 6.14 rtcsm and ramsm standby operation the standby power switch in ctm6 monitors v dd and selects either v dd and v ddsyn or v rtc for the power source of the rtcsm and ramsms, depending on the level of v dd . when v dd is within the specified operating range, the rtcsm low-power oscillator is powered by v ddsyn and the ramsms are powered by v dd . v dd also provides power to the digital logic portion of the rtcsm, therefore both v dd and v ddsyn must be kept equal to each other for normal operation. when v dd and v ddsyn are powered down, the submodules are powered by v rtc and are in standby mode. in standby mode, the rtcsm continues to keep time if enabled. however, updates to the 15-bit prescaler and 32-bit free-running counter buffer registers are halted in order to conserve power. all pio17a piosm control register $yff488 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data7 data6 data5 data4 data3 data2 data1 data0 ddr7 ddr6 ddr5 ddr4 ddr3 ddr2 ddr1 ddr0 reset: 0 0 u u u u u u 0 0 0 0 0 0 0 0 table 65 ramsm address locations static ram submodule address 32 $yff500?1e 36 $yff520?3e
mc68ck338 motorola MC68CK338TS/d 109 rtcsm registers are write protected in standby mode to prevent loss of data in runaway situations. for the same reason, the ramsms are also write protected in standby mode. if the standby mode function is not required in a given application, v rtc should be powered from the v dd and v ddsyn supply. unpredictable operation of the ramsms and rtcsm may result otherwise. 6.15 ctm6 interrupts the ctm6 is able to request numerous interrupts on the imb. each submodule that is able to request interrupts can do so with any of seven levels. each submodule that is able to request interrupts includes a 3-bit level number and a 1-bit arbitration number that is initialized by software. the 3-bit level number selects which of seven interrupt signals on the imb are driven by that submodule to create an interrupt request. of the four priority bits provided on the imb during arbitration among the modules, one of them comes from the chosen submodule, and the biusm provides the other three. thus, the ctm6 responds to two of the possible 15 arbitration numbers. during the imb arbitration process, the biusm manages the separate arbitration among the ctm6 sub- modules to determine which submodule should respond. of the submodules which have an interrupt request pending at the level being arbitrated on the imb, the submodule which has the lowest address is given the highest priority to respond. when the iarb number is not unique for a given module, simultaneous interrupts are prioritized in hard- ware according to the vector number or the submodule interrupt arbitration sequence number shown in table 66 . following the interrupt arbitration process, the ctm6 provides an 8-bit vector number. six of the eight bits are provided by the submodules. a submodule can identify two separate interrupt sources with unique interrupt vectors. the two high-order bits of the 8-bit vector are provided by the biusm. the six low-order vector bits identify the highest priority interrupt request pending in the ctm6 at the begin- ning of the arbitration cycle.
motorola mc68ck338 110 MC68CK338TS/d notes: 1. y = m111, where m is the state of the mm bit in simlcr of the siml (y = $7 or $f). 2. ?x?represents vect[7:6], which is located in the biusm module configuration register. 3. submodule interrupt arbitration number 2 is the highest priority; arbitration number 63 is the lowest priority. table 66 ctm6 interrupt priority and vector/pin allocation submodule name submodule base address 1 submodule interrupt vector number 2 submodule interrupt arbitration sequence number 3 biusm $yff400 none none cpsm $yff408 none none mcsm2 $yff410 xx000010 2 fcsm3 $yff418 xx000011 3 dasm4 $yff420 xx000100 4 dasm5 $yff428 xx000101 5 dasm6 $yff430 xx000110 6 dasm7 $yff438 xx000111 7 dasm8 $yff440 xx001000 8 dasm9 $yff448 xx001001 9 dasm10 $yff450 xx001010 10 sasm12 $yff460 xx001100 12 sasm14 $yff470 xx001110 14 rtcsm16 $yff480 xx010000 16 piosm17a $yff488 sasm18 $yff490 xx010010 18 sasm24 $yff4c0 xx011000 24 dasm26 $yff4d0 xx011010 26 dasm27 $yff4d8 xx011011 27 dasm28 $yff4e0 xx011100 28 dasm29 $yff4e8 xx011101 29 mcsm30 $yff4f0 xx011110 30 mcsm31 $yff4f8 xx011111 31 ramsm32 $yff500 ramsm36 $yff520
mc68ck338 motorola MC68CK338TS/d 111 7 electrical characteristics this section contains electrical specification tables and reference timing diagrams. notes: 1. permanent damage can occur if maximum ratings are exceeded. exposure to voltages or currents in excess of recommended values affects device reliability. device modules may not operate normally while being ex- posed to electrical extremes. 2. although sections of the device contain circuitry to protect against damage from high static voltages or elec- trical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. this parameter is periodically sampled rather than 100% tested. 4. all pins except tsc. 5. all functional non-supply pins are internally clamped to v ss for transitions below v ss . all functional pins except extal and xfc are internally clamped to v dd for transitions below v dd . 6. power supply must maintain regulation within operating v dd range during instantaneous and operating max- imum current conditions. 7. total input current for all digital input-only and all digital input/output pins must not exceed 10 ma. exceeding this limit can cause disruption of normal operation. table 67 maximum ratings num rating symbol value unit 1 supply voltage 1, 2, 3 v dd ?0.3 to + 6.5 v 2 input voltage 1, 2, 3, 4 v in ?0.3 to + 6.5 v 3 instantaneous maximum current single pin limit (applies to all pins) 1, 3, 5, 6 i d 25 ma 4 operating maximum current digital input disruptive current 5, 6, 7 v ss ?0.3 v in v dd + 0.3 i id ?500 to + 500 m a 5 operating temperature range t a t l to t h ?40 to + 85 c 6 storage temperature range t stg ?55 to + 150 c
motorola mc68ck338 112 MC68CK338TS/d table 68 thermal characteristics num characteristic symbol value unit 1 thermal resistance plastic 144-pin surface mount q ja 48 c/w the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . t j t a p d q ja () + = p d kt j 273 c + () ? = kp d t a 273 c + ()q ja p d 2 ++ =
mc68ck338 motorola MC68CK338TS/d 113 notes: 1. tested with a 32.768 khz reference. 2. all internal registers retain data at 0 hz. 3. assumes that stable v ddsyn is applied, and that the crystal oscillator is stable. lock time is measured from the time v dd and v ddsyn are valid until reset is released. this specification also applies to the period re- quired for pll lock after changing the w and y frequency control bits in the synthesizer control register (syn- cr) while the pll is running, and to the period required for the clock to lock after lpstop. 4. this parameter is periodically sampled rather than 100% tested. 5. assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. total external resistance from the xfc pin due to external leakage must be greater than 15 m w to guarantee this specification. filter network geometry can vary depending upon operating environment. 6. proper layout procedures must be followed to achieve specifications. 7. internal vco frequency (f vco ) is determined by syncr w and y bit values. the syncr x bit controls a divide-by-two circuit that is not in the synthesizer feedback loop. when x = 0, the divider is enabled, and f sys = f vco ? 4. when x = 1, the divider is disabled, and f sys = f vco ? 2. x must equal one when operating at maximum specified f sys . 8. jitter is the average deviation from the programmed frequency measured over the specified interval at max- imum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable ex- ternal clock signal. noise injected into the pll circuitry via v ddsyn and v ss and variation in crystal oscillator frequency increase the j clk percentage for a given interval. when clock jitter is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system. table 69 clock control timing (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 pll reference frequency range 1 f ref 25 50 khz 2 system frequency 2 on-chip pll system frequency range external clock operation f sys dc 4(f ref ) dc 14.4 14.4 14.4 mhz 3 pll lock time 1, 3, 4, 5, 6 t lpll 20 ms 4 vco frequency 7 f vco 2 (f sys max) mhz 5 limp mode clock frequency syncr x bit = 0 syncr x bit = 1 f limp f sys max/2 f sys max mhz 6 clkout jitter 1, 4, 5, 6, 8 short term (5 m s interval) long term (500 m s interval) j clk ?0.5 ?0.05 0.5 0.05 %
motorola mc68ck338 114 MC68CK338TS/d table 70 dc characteristics (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit 1 input high voltage v ih 0.7 (v dd )v dd + 0.3 v 2 input low voltage v il v ss ?0.3 0.2 (v dd )v 3 input hysteresis 1 v hys 0.5 v 4 input leakage current 2 v in = v dd or v ss input-only pins i in ?.5 2.5 m a 5 high impedance (off-state) leakage current 2 v in = v dd or v ss all input/output and output pins i oz ?.5 2.5 m a 6 cmos output high voltage 2, 3 i oh = ?0.0 m a group 1, 2, 4 input/output and all output pins v oh v dd ?0.2 v 7 cmos output low voltage 2 i ol = 10.0 m a group 1, 2, 4 input/output and all output pins v ol 0.2 v 8 output high voltage 2, 3 i oh = ?.4 ma group 1, 2, 4 input/output and all output pins v oh v dd ?0.5 v 9 output low voltage 2 i ol = 0.8 ma group 1 i/o pins, clkout, freeze/quot, ipipe /dso i ol = 2.65 ma group 2 and group 4 i/o pins, csboo t , bg /cs1 i ol = 6 ma group 3 v ol 0.4 0.4 0.4 v 10 three state control input high voltage v ihtsc 2.7 (v dd ) 9.1 v 11 data bus mode select pull-up current 4 v in = v il data[15:0] v in = v ih data[15:0] i msp ? ?5 m a 12 v dd supply current 5 run 6 lpstop, (stcpu = 0, external clock input frequency = max f sys ) lpstop, (stcpu = 1, external clock input frequency = max f sys ) stop 7 , (stcpu = 1, external clock input frequency = max f sys ) i dd s idd s idd s idd 46 2 18 13 ma ma ma ma 13 v rtc voltage v sb 2.2 3.6 v 14 v rtc current 8 ctm6-rtcsm oscillator enabled, v dd = v ss ctm6-rtcsm oscillator disabled, v dd = v ss v dd = v ddsyn 3 2.7 v i sb 1.0 0.200 0 m a m a m a 15 v ddsyn supply current 5 vco on, 32.768 khz crystal reference, maximum f sys external clock, maximum f sys lpstop, 32.768 khz crystal reference, vco off (stsim = 0) i ddsyn 750 1.5 300 m a ma m a 16 power dissipation 9 p d 171 mw
mc68ck338 motorola MC68CK338TS/d 115 notes: 1. applies to: ctm6 pins qsm pins irq[7:1] , reset , extal, tsc, rmc , bkpt /dsclk, ifetch /dsi 2. input-only pins: tsc, bkpt /dsclk, rxd output-only pins: csboo t , bg /cs1 , clkout, freeze/quot, ipipe /dso input/output pins: group 1: data[15:0], ifetch /dsi, all ctm6 pins except ctm31l group 2: addr[23:19]/cs[10:6] , fc[2:0]/cs[5:3] , dsa ck[1:0] , a vec , rmc , ds , as , siz[1:0],irq[7:1 , modclk, addr[18:0], r/w , berr , br /cs0 , bga ck /cs2 , pcs[3:1], pcs0/ss , txd group 3: hal t , reset group 4: miso, mosi, sck 3. does not apply to hal t and reset because they are open drain pins. does not apply to miso, mosi, sck, pcs0/ss, pcs[3:1], and txd in wired-or mode. does not apply to ctd[29:26] and ctd[10:4] in wired-or mode. 4. use of an active pulldown device is recommended. 5. total operating current is the sum of the appropriate v dd supply and v ddsyn supply current. 6. current measured with system clock frequency of 14.4 mhz, all modules active. 7. lpstop with stcpu = 1 (clock turned off at cpu32l but imb clock active) plus qsm and ctm6 stop bits set. 8. v rtc current measured when v dd and v ddsyn are equal to v ss and v rtc is equal to v sb max. 9. power dissipation is measured with a system clock frequency of 14.4 mhz, all modules active. power dissipa- tion is calculated using the following expression: p d = 3.6v (i ddsyn + i dd ) 10. input capacitance is periodically sampled rather than 100% tested. 17 input capacitance 2, 10 all input-only pins all input/output pins c in 10 20 pf 18 load capacitance 2 group 1 i/o pins, clkout, freeze/quot, ipipe /dso group 2 i/o pins and csboo t , bg /cs1 group 3 i/o pins group 4 i/o pins c l 90 100 130 200 pf table 70 dc characteristics (continued) (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ) num characteristic symbol min max unit
motorola mc68ck338 116 MC68CK338TS/d table 71 ac timing (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit f1 frequency of operation f 0 14.4 mhz 1 clock period t cyc 69.4 ns 1a eclk period t ecyc 555 ns 1b external clock input period 2 t xcyc 69.4 ns 2, 3 clock pulse width t cw 24.7 ns 2a, 3a eclk pulse width t ecw 277.5 ns 2b, 3b external clock input high/low time 2 t xchl 34.7 ns 4, 5 clkout rise and fall time t crf ?0ns 4a, 5a rise and fall time ?all outputs except clkout t rf ?0ns 6 clock high to addr, fc, size, rmc valid t chav 035ns 7 clock high to addr, data, fc, size, rmc high impedance t chazx 069ns 8 clock high to addr, fc, size, rmc invalid t chazn 0ns 9 clock low to as , ds , cs asserted t clsa 225ns 9a as to ds or cs asserted (read) 3 t stsa ?5 15 ns 9c clock low to ifetch , ipipe asserted t clia 231ns 11 addr, fc, size, rmc valid to as , cs , (and ds read) asserted t avsa 15 ns 12 clock low to as , ds , cs negated t clsn 235ns 12a clock low to ifetch , ipipe negated t clin 231ns 13 as , ds , cs negated to addr, fc size invalid (address hold) t snai 19 ns 14 as , cs (and ds read) width asserted t swa 138 ns 14a ds , cs width asserted (write) t swaw 44 ns 14b as , cs (and ds read) width asserted (fast cycle) t swdw 44 ns 15 as , ds , cs width negated 4 t sn 44 ns 16 clock high to as , ds , r/w high impedance t chsz ?9ns 17 as , ds , cs negated to r/w high t snrn 19 ns 18 clock high to r/w high t chrh 035ns 20 clock high to r/w low t chrl 035ns 21 r/w high to as , cs asserted t raaa 19 ns 22 r/w low to ds , cs asserted (write) t rasa 80 ns 23 clock high to data out valid t chdo ?5ns 24 data out valid to negating edge of as , cs (fast write cycle) t dvasn 19 ns 25 ds , cs negated to data out invalid (data out hold) t sndoi 19 ns 26 data out valid to ds , cs asserted (write) t dvsa 19 ns
mc68ck338 motorola MC68CK338TS/d 117 27 data in valid to clock low (data setup) t dicl 5ns 27a late berr , hal t asserted to clock low (setup time) t belcl 25 ns 28 as , ds negated to dsa ck[1:0] , berr , hal t , a vec negated t sndn 0 100 ns 29 ds , cs negated to data in invalid (data in hold) 5 t sndi 0ns 29a ds , cs negated to data in high impedance 5, 6 t shdi ?5ns 30 clkout low to data in invalid (fast cycle hold) 5 t cldi 19 ns 30a clkout low to data in high impedance 5 t cldh 100 ns 31 dsa ck[1:0] asserted to data in valid 7 t dadi ?8ns 33 clock low to bg asserted/negated t clban ?5ns 35 br asserted to bg asserted (rmc not asserted) 8 t braga 1t cyc 37 bga ck asserted to bg negated t gagn 12t cyc 39 bg width negated t gh 2t cyc 39a bg width asserted t ga 1t cyc 46 r/w width asserted (write or read) t rwa 174 ns 46a r/w width asserted (fast write or read cycle) t rwas 104 ns 47a asynchronous input setup time br , bga ck , dsa ck[1:0] , berr , a vec , hal t t aist 10 ns 47b asynchronous input hold time t aiht 19 ns 48 dsa ck[1:0] asserted to berr , hal t asserted 9 t daba ?5ns 53 data out hold from clock high t doch 0ns 54 clock high to data out high impedance t chdh ?5ns 55 r/w asserted to data bus impedance change t radc 55 ns 56 reset pulse width (reset instruction) t hrpw 512 t cyc 57 berr negated to hal t negated (rerun) t bnhn 0ns 70 clock low to data bus driven (show cycle) t scldd 035ns 71 data setup time to clock low (show cycle) t sclds 19 ns 72 data hold from clock low (show cycle) t scldh 10 ns 73 bkpt input setup time t bkst 19 ns 74 bkpt input hold time t bkht 13 ns 75 mode select setup time (data[15:0], modclk, bkpt )t mss 20 t cyc 76 mode select hold time (data[15:0], modclk, bkpt) t msh 0ns 77 reset assertion time 10 t rsta 4t cyc 78 reset rise time 11, 12 t rstr ?0t cyc table 71 ac timing (continued) (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit
motorola mc68ck338 118 MC68CK338TS/d notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. when an external clock is used, minimum high and low times are based on a 50% duty cycle. the minimum allowable t xcyc period is reduced when the duty cycle of the external clock varies. the relationship between ex- ternal clock input duty cycle and minimum t xcyc is expressed: minimum t xcyc period = minimum t xchl / (50% ?external clock input duty cycle tolerance). 3. specification 9a is the worst-case skew between as and ds or cs . the amount of skew depends on the relative loading of these signals. when loads are kept within specified limits, skew will not cause as and ds to fall out- side the limits shown in specification 9. 4. if multiple chip selects are used, cs width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. the cs width negated specification between multiple chip selects does not apply to chip selects being used for synchronous eclk cycles. 5. hold times are specified with respect to ds or cs on asynchronous reads and with respect to clkout on fast cycle reads. the user is free to use either hold time. 6. maximum value is equal to (t cyc / 2) + 25 ns. 7. if the asynchronous setup time (specification 47a) requirements are satisfied, the dsa ck[1:0] low to data setup time (specification 31) and dsa ck[1:0] low to berr low setup time (specification 48) can be ignored. the data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. berr must satisfy only the late berr low to clock low setup time (specification 27a) for the following clock cycle. 8. to ensure coherency during every operand transfer, bg is not asserted in response to br until after all cycles of the current operand transfer are complete. 9. in the absence of dsa ck[1:0] , berr is an asynchronous input using the asynchronous setup time (specification 47a). 10. after external reset negation is detected, a short transition period (approximately 2 t cyc ) elapses, then the siml drives reset low for 512 t cyc . 11. external assertion of the reset input can overlap internally-generated resets. to ensure that an external reset is recognized in all cases, reset must be asserted for at least 590 clkout cycles. 12. external logic must pull reset high during this period in order for normal mcu operation to begin.
mc68ck338 motorola MC68CK338TS/d 119 figure 26 clkout output timing diagram figure 27 external clock input timing diagram figure 28 eclk output timing diagram 68300 clkout tim 4 clkout 5 2 3 1 note: timing shown with respect to 20% and 70% v dd . 68300 ext clk input tim 4b extal 5b 2b 3b 1b note: timing shown with respect to 20% and 70% v dd . pulse width shown with respect to 50% v dd . 68300 eclk output tim 4a eclk 5a 2a 3a 1a note: timing shown with respect to 20% and 70% v dd .
motorola mc68ck338 120 MC68CK338TS/d figure 29 read cycle timing diagram 68300 rd cyc tim clkout s0 s1 s2 s3 s4 s5 48 27a 27 28 29 47a 21 9a 11 12 8 6 addr[23:20] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr ifetch 20 18 47b 47a asynchronous inputs halt 12a 12a 9c bkpt 9 74 73 17 14 15 13 46 31 29a
mc68ck338 motorola MC68CK338TS/d 121 figure 30 write cycle timing diagram 68300 wr cyc tim clkout s0 s1 s2 s3 s4 s5 27a 28 25 20 9 11 12 8 6 addr[23:20] fc[2:0] siz[1:0] ds cs r/w as dsack0 dsack1 data[15:0] berr halt bkpt 54 53 55 47a 26 23 9 74 73 21 14 22 14a 17 46 13 15 48
motorola mc68ck338 122 MC68CK338TS/d figure 31 fast termination read cycle timing diagram 68300 fast rd cyc tim clkout s0 s1 s4 s5 s0 18 9 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as data[15:0] 14b 8 bkpt 12 46a 30 27 73 29a 20 74 30a 29
mc68ck338 motorola MC68CK338TS/d 123 figure 32 fast termination write cycle timing diagram 68300 fast wr cyc tim clkout s0 s1 s4 s5 s0 20 9 6 addr[23:0] fc[2:0] siz[1:0] ds cs r/w as data[15:0] 14b 8 bkpt 12 46a 23 73 24 18 25 74
motorola mc68ck338 124 MC68CK338TS/d figure 33 bus arbitration timing diagram ?active bus case 68300 bus arb tim clkout s0 s1 s2 s3 s4 addr[23:0] data[15:0] 7 s98 a5 a5 a2 47a 39a 35 33 33 16 s5 as ds r/w dsack0 dsack1 br bg bgack 37
mc68ck338 motorola MC68CK338TS/d 125 figure 34 bus arbitration timing diagram ?idle bus case 68300 bus arb tim idle clkout a0 a5 addr[23:0] data[15:0] a2 a3 a0 a5 br as bg bgack 47a 33 33 47a 37 47a 35
motorola mc68ck338 126 MC68CK338TS/d figure 35 show cycle timing diagram clkout s0 s41 s42 s0 s1 s2 6 addr[23:0] r/w as 8 ds 72 data[15:0] bkpt 71 70 12 9 15 73 18 20 show cycle start of external cycle 74 s43 68300 shw cyc tim note: show cycles can stretch during clock phase s42 when bus accesses take longer than two cycles due to imb module wait-state insertion.
mc68ck338 motorola MC68CK338TS/d 127 figure 36 chip select timing diagram figure 37 reset and mode select timing diagram 68300 chip sel tim 6 6 8 11 11 25 53 54 23 55 29a 29 27 46 46 14a 12 13 15 9 9 12 14 9 18 20 18 s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 14 clkout addr[23:0] fc[2:0] siz[1:0] as ds cs r/w data[15:0] 21 21 17 17 68300 rst/mode sel tim reset data[15:0], 75 76 77 78 modclk, bkpt
motorola mc68ck338 128 MC68CK338TS/d figure 38 background debugging mode timing diagram ? serial communication notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. table 72 background debugging mode timing (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit b0 dsi input setup time t dsisu 19 ns b1 dsi input hold time t dsih 13 ns b2 dsclk setup time t dscsu 19 ns b3 dsclk hold time t dsch 13 ns b4 dso delay time t dsod ?5ns b5 dsclk cycle time t dsccyc 2t cyc b6 clkout high to freeze asserted/negated t frzan ?4ns b7 clkout high to ifetch high impedance t ifz ?4ns b8 clkout high to ifetch valid t if ?4ns b9 dsclk low time t dsclo 1t cyc 68300 bkgd dbm ser com tim b1 b3 b2 b0 b4 clkout freeze bkpt /dsclk ifetch /dsi ipipe /dso b5 b9
mc68ck338 motorola MC68CK338TS/d 129 figure 39 background debugging mode timing diagram ? freeze assertion notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. when the previous bus cycle is not an eclk cycle, the address may be valid before eclk goes low. 3. address access time = t ecyc ?t ead ?t edsr . 4. chip select access time = t ecyc ?t ecsd ?t edsr . table 73 eclk bus timing (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h ) 1 num characteristic symbol min max unit 1a eclk period t ecyc 555 ns 2a, 3a eclk pulse width t ecw 277.5 ns e1 eclk low to address valid 2 t ead ?0 ns e2 eclk low to address hold t eah 10 ns e3 eclk low to cs valid (cs delay) t ecsd 140 ns e4 eclk low to cs hold t ecsh 10 ns e5 cs negated width t ecsn 35 ns e6 read data setup time t edsr 35 ns e7 read data hold time t edhr 5ns e8 eclk low to data high impedance t edhz 130 ns e9 cs negated to data hold (read) t ecdh 0ns e10 cs negated to data high impedance t ecdz ?t cyc e11 eclk low to data valid (write) t eddw ?t cyc e12 eclk low to data hold (write) t edhw 10 ns e13 address access time (read) 3 t eacc 450 ns e14 chip select access time (read) 4 t eacs 380 ns e15 address setup time t eas 1/2 t cyc 68300 bdm frz tim b8 clkout freeze ifetch /dsi b6 b6 b7
motorola mc68ck338 130 MC68CK338TS/d figure 40 eclk timing diagram 68300 e cycle tim clkout addr[23:0] cs eclk data[15:0] e1 2a 3a e2 e5 e4 e3 e9 e7 e8 e10 e12 e14 e13 1a data[15:0] e15 e11 write read write e6 r/w
mc68ck338 motorola MC68CK338TS/d 131 notes: 1. all ac timing is shown with respect to 20% v dd and 70% v dd levels unless otherwise noted. 2. for high time, n = external sck rise time; for low time, n = external sck fall time. 3. data can be recognized properly with longer transition times as long as mosi/miso signals from external sources are at valid v oh /v ol prior to sck transitioning between valid v ol and v oh . due to process variation, logic decision point voltages of the data and clock signals can differ, which can corrupt data if slower transition times are used. table 74 qspi timing (v dd and v ddsyn = 2.7 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h 200 pf load on all qspi pins) 1 num function symbol min max unit 1 operating frequency master slave f op dc dc 1/4 1/4 system clock frequency system clock frequency 2 cycle time master slave t qcyc 4 4 510 t cyc t cyc 3 enable lead time master slave t lead 2 2 128 t cyc t cyc 4 enable lag time master slave t lag 2 1/2 sck t cyc 5 clock (sck) high or low time master slave 2 t sw 2 t cyc ?60 2 t cyc ?n 255 t cyc ns ns 6 sequential transfer delay master slave (does not require deselect) t td 17 13 8192 t cyc t cyc 7 data setup time (inputs) master slave t su 45 30 ns ns 8 data hold time (inputs) master slave t hi 0 30 ns ns 9 slave access time t a ? t cyc 10 slave miso disable time t dis ? t cyc 11 data valid (after sck edge) master slave t v 75 75 ns ns 12 data hold time (outputs) master slave t ho 0 0 ns ns 13 rise time input output t ri t ro 2 45 m s ns 14 fall time input 3 output t fi t fo 2 45 m s ns
motorola mc68ck338 132 MC68CK338TS/d figure 41 qspi timing ?master, cpha = 0 figure 42 qspi timing ?master, cpha = 1 qspi mast cpha0 13 11 6 10 12 4 4 13 12 3 2 5 1 data lsb in msb in msb out msb in msb out data lsb out port data 7 12 13 pcs[3:0] output pd miso input mosi output sck cpol=0 output sck cpol=1 output qspi mast cpha1 13 11 10 12 4 4 13 12 3 2 5 1 msb pcs[3:0] output miso input msb msb out data lsb out port data 12 13 port data mosi output data lsb in msb in 7 6 1 sck cpol=0 output sck cpol=1 output
mc68ck338 motorola MC68CK338TS/d 133 figure 43 qspi timing ?slave, cpha = 0 figure 44 qspi timing ?slave, cpha = 1 13 10 13 7 6 8 11 9 11 12 4 13 12 3 2 5 1 data lsb out pd msb out msb in msb out msb in data lsb in ss input sck cpol=0 input sck cpol=1 input miso output mosi input 4 qspi slv cpha0 qspi slv cpha1 ss input 13 12 4 12 5 11 12 6 10 9 8 data slave lsb out pd msb out msb in data lsb in 7 4 1 2 10 pd 13 3 miso output sck cpol=1 input mosi input sck cpol=0 input

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